Sandisk Technologies Inc.

Western Digital Technologies, Inc.

Ramot at Tel-aviv University Ltd.

Sandisk Il Ltd.

Comsys Communications & Signal Processing Ltd.

Sandisk Corporation

M-systems Flash Disk Pioneers, Ltd.

Romat at Tel Aviv University Ltd.

Idan Alrod

Eran Sharon

Simon Litsyn

Ariel Navon

Alexander Bazarsky

Ran Zamir

Menahem Lasser

Evgeny Mekhanik

Yan Li

Mark Murin

Stella Achtenberg

Alex Bazarsky

Alon Eyal

Omer Fainzilber

Ishai Ilani

Dana Lee

Tianhong Yan

Alon Marcu

Tz-Yi Liu

Idan Goldenberg

Yehuda Hahn

Nian Niles Yang

Mark Shlick

Rami Rom

Gerrit Jan Hemink

Seungjune Jeon

Toru Miwa

Liang Pang

Tien-Chien Kuo

Dudy David Avraham

David Rozman

Noam Presman

Nika Yanuka

Shay Benisty

Deepanshu Dutta

Nima Mokhlesi

Jianmin Huang

Raul-Adrian Cernea

Kevin M Conley

Karin Inbar

Hadas Oshinsky

Grishma Shah

David Avraham

Rajeev Nagabhirava

Damian Pablo Yurzola

Yan Dumchin

Joanna Lai

Yuri Ryabinin

Ofer Shapira

Michael Altshuler

Sergey Anatolievich Gorobets

Huai-Yuan Tseng

Itzhak Pomerantz

Jun Wan

Ehud Reshef

Jack Frayer

Julian Vlaiko

Sarath Chandran Puthenthermadam

Amir Ban

Qing Li

Eli Elmoalem

Xiaoyu Yang

Yee Lih Koh

Amul Dhirajbhai Desai

Nimrod Hermesh

Christopher John Petti

Richard Leo Galbraith

Ting Luo

Chris Avila

Abhijeet Manohar

Gautam Ashok Dusija

Mordechai Teicher

Niles Yang

Xinde Hu

Changyuan Chen

Jonas Andrew Goode

Narendhiran Chinnaanangur Ravimohan

Chris Nga Yee Avila

Yacov Duzly

Gopinath Balakrishnan

Mai Ghaly

Muralitharan Jayaraman

Lee M Gavens

Shahar Bar-Or

Rahav Yairi

Xinmiao Zhang

Opher Lieber

Yair Baram

Uri Peltz

Wanfang Tsai

Gen Pei

Henry Yip

Itshak Afriat

Lanlan Gu

A Harihara Sravan

Yigal Eli

Hanan Borukhov

Roi Kirshenbaum

Mark Fiterman

A multi-gear ECC decoder includes a high power decoder and a low power decoder. In order to significantly reduce the decoding time for high-BER codewords using a slow high power decoder, rather than decoding codewords in either slow high power or fast low power, a controller switches between slow high power decoding and fast low power decoding during the decoding process. The controller first will determine, based on a predetermined factor, whether to start decoding in slow high power or fast low power. Once a decoding power is determined, then the decoding will begin. During the decoding process the decoding transitions from a first power lever decoder to a second power level decoder. The decoding will continue in the second decoding power level after the transition, until the decoding is completed or if another switch needs to occur for insufficient decoding.

ML assisted dynamic decoding gear selection

A storage system has an inference engine that can infer a read threshold based on a plurality of parameters of the memory. The read threshold can be used in reading a wordline in the memory during a regular read operation or as part of an error handling process. Using a machine-learning-based approach to infer a read threshold can provide significant improvement in read threshold accuracy, which can reduce bit error rate and improve latency, throughput, power consumption, and quality of service. In another embodiment, a circuit-bounded array is used to manage updates to time and temperature tag information and to infer read thresholds.

Storage system and method for circuit-bounded-array-based time and temperature tag management and inference of read thresholds

A storage system has an inference engine that can infer a read threshold based on a plurality of parameters of the memory. The read threshold can be used in reading a wordline in the memory during a regular read operation or as part of an error handling process. Using this machine-learning-based approach to infer a read threshold can provide significant improvement in read threshold accuracy, which can reduce bit error rate and improve latency, throughput, power consumption, and quality of service. In another embodiment, a storage system is configured to use a binary full-depth symmetrically-sorted tree to infer a read threshold based on a plurality of parameters of the memory.

Storage system and method for implementation of symmetric tree models for read threshold calibration

A storage system has an inference engine that can infer a read threshold based on a plurality of parameters of the memory. The read threshold can be used in reading a wordline in the memory during a regular read operation or as part of an error handling process. Using this machine-learning-based approach to infer a read threshold can provide significant improvement in read threshold accuracy, which can reduce bit error rate and improve latency, throughput, power consumption, and quality of service.

Storage system and method for inference of read thresholds based on memory parameters and conditions

The present disclosure generally relates to estimating when data to be written will be read or re-written prior to actually writing the data to the memory device. The estimating can be used to smartly route the data to the appropriate memory location at the writing stage or to evict the data from a hot memory location to a colder memory location. To perform the estimating, typical traces or data may be used as may the metadata of the data. Separating data according to the data 'temperature' (i.e. the expected access time and frequency), and usage to optimize the SLC partition usage has meaningful impact on several storage metrics such as performance and endurance.

Hot-cold chunks soft-prediction during programming

A system and method for calibrating read threshold voltages includes performing a plurality of read operations, determining to perform a read level tracking method, and performing the read level tracking method. The determining may be based on a temperature change or a bit error rate (BER). The read level tracking method includes determining the BER of an indicative word line, determining an adjusted read threshold level based on the BER, and adjusting read threshold levels according to the adjusted read threshold level.

Read threshold calibration for cross-temperature long, sequential reads

The disclosure relates in some aspects to on-chip processing circuitry formed within the die of a non-volatile (NVM) array to perform data searches. In some aspects, the die includes components configured to sense wordlines of stored data in the NVM array by applying voltages on the wordlines serially, and then search for an input data pattern within the serially-sensed wordlines. In some examples, the components of the die include latches and circuits configured to perform bitwise latch logic search operations. In other examples, the search components are configured with under-the-array or next-to-the-array dedicated search circuitry that uses registers and/or random access memory (RAM). Other aspects relate to a separate controller device for controlling the on-chip NVM search operations. For example, the controller may determine whether to search for data using search components of the NVM die or processors of the controller based, e.g., on a degree of fragmentation of data.

On-chip non-volatile memory (NVM) search

An apparatus includes a first encoder circuit configured to compress a block of data using dictionary based compression and a second encoder circuit connected to the first encoder circuit to receive the compressed block of data from the first encoder circuit. The second encoder circuit is configured to further compress the compressed block of data according to a codebook. The codebook is based on a distribution of data of a prior block of data or a distribution of data of a portion of the block of data that is less than the block of data. The operation of the second encoder circuit overlaps with the operation of the first encoder circuit to achieve high throughput and avoid the need for a large block of memory (e.g., SRAM) to occupy the data in flight until the second encoder circuit can start.

Data compression with entropy encoding

Low-density parity-check (LDPC) coding based on memory cell voltage distribution (CVD) in data storage devices. In one embodiment, a memory controller includes a memory interface configured to interface with a non-volatile memory; and a controller. The controller is configured to receive a plurality of data pages to be stored in the non-volatile memory, and transform the plurality of data pages into a plurality of transformed data pages. The controller is further configured to determine a plurality of parity bits based on the plurality of transformed data pages, and store the plurality of data pages and the plurality of parity bits in the non-volatile memory.

Memory matched low density parity check coding schemes

A storage system has a memory with memory cells that can store a non-power-of-two number of states. A map is used to distribute data bits in the memory. The map can be a modified version of a quadrature amplitude modulation (QAM) map. The mapping can be done by a controller in the storage system or by the memory die. Performing the mapping in the memory die can reduce data traffic between the controller and the memory die, which can provide an improvement to performance and power consumption.

Storage system and method for multi-cell mapping

A non-volatile memory system comprises an integrated memory assembly in communication with a memory controller. The integrated memory assembly includes a memory die bonded to a control die. The control die includes one or more control circuits for controlling the operation of the memory die. The control circuits are configured to receive a request to copy data on the memory die, read codewords on the memory die in response to the request, decode the codewords to identify errors in the codewords, correcting the errors in the codewords, and program the codewords back into the memory die. In one embodiment, the codewords read are stored in the memory die as single bit per memory cell data and the codewords programmed back into the memory die after correcting errors are programmed as multiple bit per memory cell data.

On-chip-copy for integrated memory assembly

Effective use of cyclic redundancy check (CRC) signatures is achieved where each sector of a flash management unit (FMU) has a distinct CRC signature. The CRC signatures are XORed together to create a total CRC signature for the FMU. When a host device updates a single sector of the FMU, the CRC signature for the updated single sector can be changed by removing the old CRC signature corresponding to the single sector and replacing the old CRC signature with a new CRC signature corresponding to the updated single sector. The old CRC signature is XORed from the total CRC signature and then the new CRC signature is XORed with the remaining CRC signatures to create a new total CRC signature. In so doing, data integrity is ensured.

Data integrity protection with partial updates

A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to receive a command, such as from a host device, to write data to the memory device, perform toggle mode (TM) encoding on the data, and send the TM encoded data to the memory device. The memory device is configured to receive the TM encoded data, decode the TM encoded data, and write the decoded data to a location within the memory device. The memory device is further configured to receive a read command to read data from a location within the memory device, read the data, TM encode the data, and send the TM encoded data to the controller. The controller is configured to receive and decode the TM encoded data, and send the decoded data to a host device.

Toggle mode (&#x2122;) coding with circuit bounded array memory

Technology for two-sided adjacent memory cell interference mitigation in a non-volatile storage system is disclosed. During reading of target memory cells, the storage system applies a suitable magnitude read pass voltage to a first unselected word line adjacent to a target word line to compensate for interference from adjacent cells on the first unselected word line while applying a suitable magnitude read reference voltage to the target word line to compensate for interference from adjacent cells on a second unselected word line on the other side of the target word line. The read pass voltage may compensate for interference due to charge being added to when programming cells on the first unselected word line after programming the target cells. The read reference voltage may compensate for interference due to charge movement near the target cells that results from charge stored in the cells on the second unselected word line.

Two-sided adjacent memory cell interference mitigation

A storage apparatus includes non-volatile memory cells formed on a memory die, each memory cell configured to hold bits of data, and a control circuit formed on the memory die. The control circuit is configured to calculate parity data for data to be stored in the memory cells and program the memory cells to first distributions. The control circuit is also configured to read the memory cells in the first distributions, recover the data from results of reading the memory cells in the first distributions combined with the parity data, and further program the memory cells from the first distributions to second distributions to store the data. In some cases, the recovered data may have a high bit error rate. To handle higher bit error rates, the use of soft bit data is incorporated into an encoded foggy-fine scheme.

Nonvolatile memory with encoding for foggy-fine programming with soft bits

Growing community of inventors

Herzliya, Israel

Idan Alrod