Panasonic Corporation

Panasonic Intellectual Property Management Co., Ltd.

Ichirou Takahashi

Takumi Mikawa

Takeshi Takagi

Yoshio Kawashima

Satoru Mitani

Zhiqiang Wei

A variable resistance element including: a first electrode; a second electrode; and a variable resistance layer having a resistance value which reversibly changes according to electrical signals applied, wherein the variable resistance layer includes a first variable resistance layer comprising a first oxygen-deficient transition metal oxide, and a second variable resistance layer comprising a second transition metal oxide having a degree of oxygen deficiency lower than a degree of oxygen deficiency of the first oxygen-deficient transition metal oxide, the second electrode has a single needle-shaped part at an interface with the second variable resistance layer, and the second variable resistance layer is interposed between the first variable resistance layer and the second electrode, is in contact with the first variable resistance layer and the second electrode, and covers the single needle-shaped part.

Variable resistance element and method of manufacturing the same

A method of manufacturing a nonvolatile memory device includes: forming a tantalum oxide material layer including an oxygen-deficient transition metal oxide; forming a tantalum oxide material layer including a transition metal oxide and having a degree of oxygen deficiency lower than a degree of oxygen deficiency of the tantalum oxide material layer; and exposing, after the forming of a tantalum oxide material layer, the tantalum oxide material layer to plasma generated from a noble gas.

Method of manufacturing nonvolatile memory device

Provided is a method for manufacturing a variable resistance nonvolatile storage device, which prevents electrical conduction between lower electrodes and upper electrodes of variable resistance elements in the memory cell holes. The method includes: forming lower copper lines; forming a third interlayer insulating layer; forming memory cell holes in the third interlayer insulating layer, an opening diameter of upper portions of the memory cell holes being smaller than bottom portions; forming a metal electrode layer on the bottom of each memory cell holes by sputtering; embedding and forming a variable resistance layer in each memory cell hole; and forming upper copper lines connected to the variable resistance layer embedded and formed in each memory cell hole.

Growing community of inventors

Kyoto, Japan

Ichirou Takahashi