Renesas Electronics Corporation

Nec Electronics Corporation

Ichirou Mizuguchi

Hiroshi Furuta

Shinji Takeda

Kenjyu Shimogawa

Junji Monden

A DRAM device includes plural N-channel MIS transistors arranged in a matrix over a P well, and a plurality of capacitors formed corresponding to the plurality of N-channel MIS transistors, and plural word lines formed corresponding to each row of the plurality of N-channel MIS transistors, and a plurality of bit lines formed corresponding to each column of the plurality of N-channel MIS transistors, and a Pdiffusion layer formed extending in the direction that the plurality of word lines extend and supplied with a p well voltage potential.

DRAM device

An integrated circuit apparatus includes a SRAM cell array having a plurality of memory cells formed of CMOSFET arranged lattice-like. The SRAM cell array has a pair of power line and ground line in each of 1-bit sequences. The integrated circuit apparatus also includes a detector detecting the occurrence of latch-up for each 1-bit sequence and outputting a detection signal, and a power controller controlling a power supply voltage to the power line for each 1-bit sequence. The power controller reduces a voltage to be supplied to the power line in the 1-bit sequence where latch-up is occurring down to a predetermined value according to the detection signal.

Growing community of inventors

Kanagawa, Japan

Ichirou Mizuguchi