Kabushiki Kaisha Toshiba

Ichiro Yoshii

Mariko Takagi

Kaoru Hama

Naoki Ikeda

Hiroaki Yasuda

Yoshio Ozawa

Katsuya Okumura

Kikuo Yamabe

Hiroshi Hatano

Kazuhiko Hashimoto

Hiroyuki Kamijoh

Satoru Takatsuka

A first electrode layer is formed on a semiconductor substrate, and surfaces other than a top surface thereof are buried in an insulation film, and the top surface makes the same surface as that of the insulation film. An antifuse insulation film is formed on a flat surface including the top surface of the first electrode layer. A second electrode layer is formed on the antifuse insulation film. An antifuse portion is formed by self-alignment at a cross point between the first and second electrode layers.

Inter-metal-wiring antifuse device provided by self-alignment

A semi conductor device is provided having the following arrangement. A first electrode is formed on the major surface of a semiconductor substrate and comprises a first Al connection layer formed over the semiconductor substrate and a barrier metal layer provided on, and electrically connected to, the first Al connection layer and serving as a barrier against the Al. An insulating film is formed over the semiconductor substrate so as to cover the first electrode. An opening is formed in the insulating film so as to partially expose the first electrode. An antifuse film is formed in a manner to partially cover the insulating film and contact with the barrier metal layer of the first electrode with the opening therebetween. The antifuse film is formed of silicon nitride whose nitrogen/silicon atomic composition ratio ranges from 0.6 to 1.2. A second electrode is formed over the antifuse film and comprised of a barrier metal layer serving as a barrier against the Al.

Semiconductor device equipped with antifuse elements and a method for

In a semiconductor device including an anti-fuse element, a first electrode layer is formed on a semiconductor substrate. A first insulating layer is formed only on the first electrode layer for insulating the first electrode layer. An anti-fuse insulating film is coated on at least one side wall portion of each of the first electrode layer and the first insulating layer. A second electrode layer is formed on the anti-fuse insulating film, and the first and second electrode layers and the anti-fuse insulating film constitute the anti-fuse element.

Semiconductor device including anti-fuse element and method of

In a semiconductor device having at least two conductive layers disposed close to each other on an element isolating insulation film formed on a first P-type region, a second P-type region is formed in a region of the first P-type region which is between the two conductive layers. The impurity concentration of the second P-type diffusion region is higher than the first P-type region. A region of the element isolating insulation film which is on the second P-type diffusion region is thin to form a thin insulation film. With the features, no inversion layer is formed in the region of the first P-type region where the second P-type diffusion region is formed. As a result, the inversion layers under the conductive layers will not be in contact with each other.

Semiconductor device

A semiconductor device is provided having the following arrangement. A first electrode is formed on the major surface of a semiconductor substrate and comprises a first Al connection layer formed over the semiconductor substrate and a barrier metal layer provided on, and electrically connected to, the first Al connection layer and serving as a barrier against the Al. An insulating film is formed over the semiconductor substrate so as to cover the first electrode. An opening is formed in the insulating film so as to partially expose the first electrode. An antifuse film is formed in a manner to partially cover the insulating film and contact with the barrier metal layer of the first electrode with the opening therebetween. The antifuse film is formed of silicon nitride whose nitrogen/silicon atomic composition ratio ranges from 0.6 to 1.2. A second electrode is formed over the antifuse film and comprised of a barrier metal layer serving as a barrier against the Al.

A method of screening a semiconductor device. A silicon wafer having gate electrodes formed on the gate oxide film is prepared. An insulating layer is deposited on the silicon wafer. Gate electrode portions of a group of transistors to be tested are exposed. A conductive layer is deposited on the silicon wafer having exposed gate electrodes. The conductive layer is patterned to be a wiring layer so that the gate electrodes of a group of the transistors can be electrically connected to each other. The chip area to be tested is irradiated with light having intensity enough to generate a required quantity of carriers in a depletion layer between a well and a substrate. A predetermined test voltage is applied between the wiring layer and the substrate of the silicon wafer during irradiation of the light to measure current flowing through the wiring layer and the gate oxide film. An abnormality of the gate oxide film can be detected on the basis of the measured current value. The screening method may be conducted before the completion of forming the gate electrodes. Further, gate electrode portions not to be used by a user may not be electrically connected to the gate electrode portions to be used.

Method of screening semiconductor device

A semiconductor integrated circuit device formed on the basis of the design rules of 0.5 .mu.m or less contains a MOS transistor. The MOS transistor is formed at the main surface region of the semiconductor substrate. If the effective gate area of the MOS transistor is S2 and the area of a contact hole made in an interlayer insulating film on the gate electrode of the MOS transistor is S1, the relationship expressed as S1/S2.ltoreq.1.8 is established. The contact hole is made by RIE techniques.

Growing community of inventors

Kawasaki, Japan

Ichiro Yoshii