Matsushita Electric Industrial Co., Ltd.

Panasonic Intellectual Property Management Co., Ltd.

Matsushita Electronics Corporation

Panasonic Corporation

Ichiro Yamane

Satoshi Fukumoto

Takafumi Tokuhiro

Hiroaki Fujimoto

Takayuki Yoshida

Tadaaki Mimura

Yoshiaki Kasuga

Takio Yamashita

Toshio Matsuki

Kazuhiko Matsumura

Tetsuo Kawakita

Takashi Otsuka

Shigeyuki Komatsu

Hirokuni Fujiyama

Shinji Ishikawa

Kazuhisa Raita

Toshifumi Hamaguchi

Yoshitaka Kitao

Shinji Miyamoto

Takahiro Inauchi

A vehicle state determination device includes an input unit and a controller. The input unit receives sidewalk information indicating a state of a sidewalk region which a moving body passes through and roadway information indicating a state of a roadway region adjacent to the sidewalk region. The controller determines whether or not a sidewalk entering operation is possible based on the sidewalk information and the roadway information. The sidewalk entering operation is an operation in which a vehicle trying to enter the roadway region by crossing the sidewalk region enters the sidewalk region.

Vehicle state determination device and vehicle state determination method

A determination device includes an input unit and a controller. The input unit receives information on a sidewalk area and information on a target object recognized in the sidewalk area. The sidewalk area exists between a position where a vehicle is present and a non-sidewalk area. The controller (i) divides the sidewalk area into a plurality of partial areas including at least a first partial area and a second partial area based on the information on the sidewalk area, the first partial area being closest to the vehicle among the plurality of partial areas, and the second partial area being adjacent to the non-sidewalk area, and (ii) determines, based on the information on the target object, at least one partial area among the plurality of partial areas to be a range where the vehicle is allowed to enter.

Determination device and determination method

A control device for an autonomous driving vehicle includes a first input section, a second input section, and a travel state determination section. The first input section acquires a detection signal of a first sensor that detects another vehicle approaching the intersection. The second input section acquires a detection signal of a second sensor that detects at least one of a gesture of a driver of the other vehicle, a voice of the driver of the other vehicle, a motion of the other vehicle, and a radio signal output from the other vehicle. The travel state determination section generates, upon detection of the other vehicle based on the detection signal of the first sensor, a travel command signal for allowing or restricting entry of the autonomous driving vehicle into the intersection in accordance with an action of the other vehicle predicted based on the detection signal of the second sensor.

Control device and method for controlling autonomous driving vehicle

A vehicle situation determination device includes an input unit and a controller. The input unit receives information about a recognition result of recognizing one or a plurality of moving objects existing in a sidewalk region ahead of a vehicle in an advancing direction. The controller determines, based on the recognition result, that the vehicle is allowed to enter a passing scheduled region in a time period of a sparse state when a transition is made from the sparse state into a dense state. The sparse state is a state where density of the one or plurality of moving objects existing in the passing scheduled region is lower than or equal to a predetermined value. The dense state is a state where the density is higher than the predetermined value.

Vehicle situation determination device and vehicle situation determination method

A voltage detection circuit includes a reference voltage and current supply configured to generate a reference voltage and a reference current; a switching element configured to shift from an off-state to an on-state when the reference voltage is higher than a predetermined threshold voltage; a current mirror circuit allowing a current corresponding to the reference current to flow through the switching element in the on-state; a capacitive element coupled in series to the current mirror circuit and charged with the current flowing through the switching element; and an inverter configured to output an enable signal activated based on a terminal voltage of the capacitive element.

Voltage detection circuit

An oscillator circuit comprises a piezoelectric vibrator, an amplifier device including inverters provided in a plurality of stages, and an inverter control device. The inverters provided in the plurality of stages includes a performance-variable inverter configured which is operational in both of an initial phase of oscillation startup and a post-startup phase where the oscillation is stabilized and capable of a variable performance depending on whether the initial phase of oscillation startup or the post-startup phase where the oscillation is stabilized, and an ON/OFF inverter which is operational in the initial phase of oscillation startup and disconnected in the post-startup phase where the oscillation is stabilized. The inverter control device have the performance-variable inverter and the ON/OFF inverter both operational and lowers the performance of the performance-variable inverter in the initial phase of oscillation startup, and the inverter control device disconnects the ON/OFF inverter and increases the performance of the performance-variable inverter in the post-startup phase where the oscillation is stabilized.

Oscillator circuit

A combination memory device including a static random access memory (SRAM) and a read only memory (ROM) comprises first memory cells and second memory cells arranged in rows and columns, in which each of the first memory cells includes an SRAM cell and a ROM cell and is arranged adjacent to at least one of the second memory cells, and each of the second memory cells includes an SRAM cell and does not include a ROM cell.

Memory device including combination SRAM-ROM cells and SRAM cells alternately arranged and semiconductor device including the memory device

A differential amplifier circuit includes: a differential transistor pair composed of first and second transistors; a first resistance connected to a junction point of the first and second transistors at one terminal and to a first voltage node at the other terminal; second and third resistances provided between the first and second transistors, respectively, and a second voltage node; and first and second passive circuits respectively connected to the second and third resistances, the load characteristics of the passive circuits changing according to a control signal supplied. A ring oscillator is composed of a plurality of such differential amplifier circuits connected in a loop.

Differential ring oscillator

An analog-digital converter includes an analog switch on a semiconductor substrate, the analog switch having a P-channel transistor and an N-channel transistor; and a capacitive element having a first electrode and a second electrode. The first electrode and the second electrode are formed in a region in a layer different from a layer of the analog switch, the region extending over the analog switch. The first electrode and the second electrode have a comb-shaped pattern different from an arrangement pattern of the source regions and the drain regions of the P-channel transistor and the N-channel transistor.

Analog-digital converter

A semiconductor integrated circuit including one or a plurality of external functional blocks; a nonvolatile memory having a logical content as to whether to validate or invalidate the external functional blocks; and a logical circuit validating or invalidating an input and an output to each external functional block in accordance with the logical content of the memory, wherein a user is allowed to validate use of a necessary external functional block and to invalidate use of an unnecessary external functional block.

Semiconductor integrated circuit

A data processor includes first and second devices that are coupled together via a signal path. The first device includes a first arithmetic unit. The first arithmetic unit performs an arithmetic operation on data to obtain a first result during an operation cycle, in which the first device transfers the data to the second device through the signal path. The first arithmetic unit outputs the first result onto the signal path during an idle cycle in which no data is transferred through the signal path. The second device includes second arithmetic unit and comparator. The second arithmetic unit performs the same type of arithmetic operation on the data, transferred through the signal path in the operation cycle, to obtain a second result. The comparator compares the first result, transferred through the signal path in the idle cycle, to the second result and outputs a comparison result.

Data processor

The present invention reduces crosstalk, which occurs as a result of interference between signals running in each of respective wiring layers of a first semiconductor chip and a second semiconductor chip stacked surface to surface with a small gap. The semiconductor device includes a first semiconductor chip 1 having a first electrode pad 2 and a first wiring layer 9 in the main surface, and a second semiconductor chip 5 having a second electrode pad 6 and a second wiring layer 10 in the main surface confronting the first semiconductor chip. A bump 4 is provided for electrically coupling the first electrode pad 2 and the second electrode pad 6 together. An insulation layer 8 is disposed between the main surfaces of first semiconductor chip 1 and second semiconductor chip 5. An electro-conductive layer 7 is disposed between the main confronting surfaces of the first semiconductor chip and the second semiconductor chip.

Structure of chip on chip mounting preventing from crosstalk noise

The main surface of a first semiconductor chip having a first functional element is formed with first testing electrodes for testing the electrical characteristics of the first functional element and first connecting electrodes electrically connected to the first functional element. The main surface of a second semiconductor chip having a second functional element is formed with second testing electrodes for testing the electrical characteristics of the second functional element and second connecting electrodes electrically connected to the second functional element. The first semiconductor chip and the second semiconductor chip are integrated by using an insulating resin, with first bumps formed on the first connecting electrodes being bonded to third bumps formed on the second connecting electrodes.

Semiconductor device and method of manufacturing the same

A microcomputer chip is formed with a CPU core, a peripheral circuit, a built-in ROM, and a built-in RAM. An emulation functional chip is formed with an emulation control circuit for controlling the whole process of emulation. First electrode pads formed on the functional surface of the microcomputer chip are electrically interconnected to second electrode pads formed on the functional surface of the emulation functional chip with connecting bumps interposed therebetween. The microcomputer chip and the emulation functional chip are modularized using an insulating resin with the first electrode pads being connected to the second electrode pads.

Growing community of inventors

Kyoto, Japan

Ichiro Yamane