Semiconductor Energy Laboratory Co., Ltd.

Tdk Corporation

Tkd Corporation

Ichiro Takayama

Michio Arai

Mitsufumi Codama

Naoya Sakamoto

Yukio Yamauchi

Kazushi Sugiura

Isamu Kobori

Mitsunori Sakama

Takeshi Fukada

Takashi Inushima

Nobumitsu Amachi

Shunpei Yamazaki

Kazuki Iwaya

Kazutaka Tamaki

Takashi Fuki

Ryosuke Hayasaki

Toshiki Murayama

A switching power supply apparatus is provided which reduces the time of application of an input voltage to a choke to suppress a peak current flowing through switch elements when a primary or secondary voltage is 0 V (or a voltage near 0 V). A DAB converter or switching power supply apparatus performs phase control to change at least either a first conduction width or a second conduction width of pairs of diagonally-arranged switch elements, constituting a primary full bridge circuit. The first conduction width is a time width in which a pulse for driving the first switch element and a pulse for driving the fourth switch element overlap temporally. The second conduction width is a time width in which a pulse for driving the second switch element and a pulse for driving the third switch element overlap temporally.

Switching power supply apparatus

A multiple power supply integration apparatus measures electric power and stability of power supplies, outputs thereof having irregularity. Based on measured values of the electric power and the stability, certainty of entire supply of the electric power when a use allocation rate of the power supplies is changed is indexed as an evaluation value. The multiple power supply integration apparatus adjusts each converter according to a use allocation rate corresponding to a largest evaluation value, thereby adjusting a magnitude of the electric power supplied from each power supply to a common power line.

Multiple power supply integration apparatus, multiple power supply integration system, and multiple power supply integration program

An active matrix type flat-panel display device includes a flat substrate, a plurality of light emissive elements arranged two dimensionally along columns and lines on the flat substrate, a plurality of selection switches formed on the flat substrate, for sequentially selecting the light emissive elements to provide video signals thereto, selection signal generation circuits for providing selection signals which drive the selection switches in sequence so as to two dimensionally scan the light emissive elements, and a selection signal control circuit for preventing the selection signals from being output from the selection signal generation circuits for a predetermined period of time so as to eliminate overlap between the selection signals.

Active matrix type flat-panel display device

A color image display system including a thin-film display device is provided. The device is driven by a current for each pixel of the device and is designed to display colors corresponding to a plurality of color signals. The display system includes a color signal converter for converting the color signal ratio of the plurality of color signals of a color signal source to a ratio of signals suitable for the colors of the thin-film display device. In this way, the color image display system provides an improved image quality, even when colors of light emitted from the thin-film display device are slight variations from NTSC or other image signals, or the current/luminance conversion efficiencies for various colors are not the same level.

Color image display system

An image display device having a plurality of pixcels with uniform light intensity comprises an organic EL element (3), a bias FET (2) for emit current control of said EL element, a capacitor (4) coupled with a gate electrode of said bias FET (2) for holding a signal, and a select FET (1) for selectively writing a signal to said capacitor (4), wherein the value S of said bias FET (2) is larger than that of said select FET (1).

Image display device

An image display system having a plurality of light emitting cells (EL.sub.11 -EL.sub.44) each having a pair of Electro-Luminescence elements (e.sub.1, e.sub.2) coupled in parallel with each other with opposite polarities. The light emitting cells are arranged on a cross point of a matrix, which is addressed through an active addressing method in which a plurality of rows of the matrix are selected simultaneously, and alternate voltage is applied to the matrix.

Organic electroluminescent image display device

A thin film transistor which includes an insulation base, first and second gate electrodes, first and second insulation layers, an active layer of semiconductor material, a source electrode and a drain electrode, in which a lateral length of the first gate electrode is narrower than a lateral length of the second gate electrode. Also, the first gate is electrically insulated from the active layer of semiconductor material by the first insulation layer so that the drain current saturates in a high drain voltage region.

Thin film transistor for controlling a device such as a liquid crystal

An image display device which is not affected by image control signal for other pixels and gives adjustable intensity based upon control signal is provided. The image display device has a thin film pixel element EL, a non-linear element 5 for emit control of said thin film pixel element EL, a signal hold capacitor C coupled with a gate electrode of said non-linear element 5, another non-linear element 6 for writing data into said capacitor C, and a resistor R coupled between said capacitor C and a fixed potential source. The resistance of said resistor R is larger than ON resistance and smaller than OFF resistance of said non-linear element 6 for data writing.

Image desplay device

In forming a thin film transistor (TFT) having an offset structure or a lightly doped drain (LDD) structure, a blocking material having a lower etching rate than that of a material constructing a gate electrode is formed. By using the blocking material as a mask, a gate electrode material is side-etched selectively to form gate electrodes. The blocking material is processed selectively and remains in a drain region side. Also, an offset region or an LDD region is formed under the blocking material by performing an impurity ion implantation. On the other hand, after the gate electrodes are formed, a resist is added and then light exposure is performed from a source region side using a light blocking material as a mask, so that the resist remains in a drain region side of the gate electrode. Also, by implanting an impurity ion, an offset region or an LDD region is formed in the drain region side.

Method for manufacturing a semiconductor device

A thin film transistor comprises a dielectric substrate (1), a semiconductor layer (3) of poly-crystalline silicon layer having a drain region (8), an active gate region (4, 8-0), and a source region (7) placed on said substrate (1), a drain terminal (10) and a source terminal (10A) connected to said respective regions for external connection, a gate electrode (6) coupled with a part of said gate region (4) through a dielectric layer (4A), wherein length (d) of said gate electrode (6) is shorter than the length of gate region (4 plus 8-0), so that an offset region (8-0), where no gate electrode faces with said gate region, is produced.

Thin film transistor

A substrate (1) has a surface covered with an insulation layer (2), on which an active layer (3') made of non-single crystal silicon through thin film technique is provided. A gate electrode layer (5') is partially provided on said active layer through a gate insulation layer (4). Said active layer (3') is subject to injection of P-type or N-type impurities to provide an image sensor of MOS structure. Bias potential is applied to a gate electrode so that a circuit between a source and a drain is in an On state, so that input light through said substrate or said gate electrode is applied to said active layer, and electrical output depending upon said input light is obtained from said source electrode or said drain electrode. Other MOS transistors for switching element and/or shift registers for operating said image sensor are provided on said substrate (1). Said active layer (3') is obtained by crystallizing said amorphous silicon layer through a laser anneal process or a high temperature anneal process, and hydrogenation process, and the trap density of said active layer is less than 5.times.10.sup.11 /cm.sup.2. Optical response time is short, less than 500 .mu.sec, so, high speed operation ten times as high as that of a prior image sensor is possible.

Growing community of inventors

Kanagawa, Japan

Ichiro Takayama