Sharp Kabushiki Kaisha Corporation

Other

Ichiro Shiraki

Yasushi Kubota

Tamotsu Sakai

Keisuke Yoshida

Kazuhiro Maeda

Hiroshi Yoneda

Mutsumi Nakajima

Hirofumi Katsuse

Shoichi Andou

Hajime Washio

Yasuyoshi Kaise

Keiichi Ina

Shingo Jogan

Masayuki Inoue

Kenichi Katoh

Osamu Sasaki

Manabu Matsuura

Jun Koyama

Yoshitaka Yamamoto

Hiromi Katoh

Kouji Kumada

Shuji Nishi

Shinsaku Shimizu

Sachio Tsujino

Junichi Yamada

Yousuke Nakagawa

Hiroaki Sugiyama

Nobuhiro Kuwabara

Zhang Hongyong

A display device includes a photosensor () in a pixel region () of an active matrix substrate (). The photosensor () includes a photodetection element, reset signal wiring that supplies a reset signal RS to the photosensor (), readout signal wiring that supplies a readout signal RW to the photosensor (), and a sensor switching element for reading out the potential of the storage node to output wiring as sensor circuit output, the potential of the storage node having changed in accordance with the amount of light received by the photodetection element in a sensing period, the sensing period being from when the reset signal is supplied until when the readout signal is supplied. The potential of wiring having a parasitic capacitance with the storage node is fixed to a predetermined potential Vat least either one of immediately before the readout signal RW and immediately before the reset signal RS.

Display device

In one embodiment of the present invention, a display panel drive circuit includes a plurality of circuit blocks each of which includes former circuits and latter circuits. In each of the circuit blocks in the display panel drive circuit, a signal is transmitted from the former circuits to the latter circuits. Further, the display panel drive circuit includes an inter-block shared wire which allows respective two of the circuit blocks adjacent to each other to be connected to each other. Furthermore, in the display panel drive circuit, the signal of the respective two of the circuit blocks adjacent to each other is transmitted in a time division manner, via the inter-block shared wire. This eliminates the need for an external memory or an arithmetic circuit, thereby making it possible to reduce the area of a circuit in a driver.

Display panel drive circuit and display

The present invention aims to provide a monolithic driver-type display device capable of reducing circuit scale of a sampling circuit, and keeping low power consumption by directly driving a source driver with an externally provided video signal. In the monolithic driver-type display device having a display portion for displaying video and circuits for driving the display portion formed on the same insulating substrate, a plurality of sampling switches are provided in association with a plurality of pieces of bit data contained in externally inputted digital video signals. The sampling switches are opened/closed based on sampling signals, thereby sampling the digital video signals for each piece of the bit data and converting the signals into parallel format for output to data lines. The outputted digital video signals charge parasitic capacitances on the data lines and are held therein.

Monolithic driver-type display device

A shield electrode is provided in the vicinity of a pixel electrode and source bus lines. The shield electrode may be provided in the same layer as gate bus lines, or in the same layer as the source bus lines. The shield electrode may be surrounded by an insulating material, or may be connected to a line other than the source bus lines. By providing the shield electrode, it is possible to reduce a source-drain parasitic capacitance between a pixel electrode and a source bus line.

Liquid crystal display device having source-drain parasitic capacitances of a delta arrangement

In a photosensor in the pixel region of an active matrix substrate, the potential of a storage node is read out to output wiring as sensor circuit output, the potential of the storage node having changed in accordance with the amount of light received by a photodetection element in a sensing period, the sensing period being from when a reset signal (RS) is supplied until when a readout signal (RW) is supplied. A sensor startup period whose length is greater than or equal to the length of the sensing period is provided after a sensor data unnecessary period in which the sensor circuit output is not necessary, and furthermore before a valid sensor data period in which the sensor circuit output is necessary, and the sensor circuit output is read out in the valid sensor data period from the photosensor to which the reset signal was applied in the sensor startup period.

In a multi-gap semi-transmissive liquid crystal display device, the width of a black matrix () is made larger above the region between adjacent ITO transparent electrodes () and is made smaller above the region between adjacent Al reflective electrodes (). This enables a transmissive portion to offer a display with high contrast that does not suffer from afterimage or the like by shielding light from the domain lying between the adjacent pixels, and the reflective portion to offer a brighter display by increasing the aperture ratio thereof by making the black matrix width as small as possible or forming no black matrix.

Liquid crystal display device

A first electrode substrate of the present invention includes a first signal line, a second signal line, a third signal line, a first pixel electrode, a second pixel electrode, and a third pixel electrode. The first signal line, the second signal line and the third signal line extend in a first direction and in parallel to one another. The first pixel electrode is electrically connected to the first signal line. The second pixel electrode is adjacent to the first pixel electrode in the first direction, and is electrically connected to the second signal line. The third pixel electrode is adjacent to the second pixel electrode in the row direction, crossing the first direction, via the second signal line therebetween, and is electrically connected to the third signal line. A capacitance value of a parasitic capacitor formed between the first pixel electrode and the second pixel electrode is smaller than a capacitance value of a parasitic capacitor formed between the first pixel electrode and the third pixel electrode.

Electrode substrate and display device including the same

A CMOS logical circuit comprises two electric current paths each of which has circuits consisting of n-type and p-type transistors. In a circuit consisting of n-type or p-type transistors, one electric current path is provided with a circuit having the same construction as that of a circuit having an n-type transistor of a CMOS logical circuit outputting a logical operation result similar to that of this logical circuit, and the other electric current path is provided with a circuit having the same construction as that of a circuit having a p-type transistor of the CMOS logical circuit outputting a logical operation result similar to that of this logical circuit. In another circuit consisting of the other channel type, a gate electrode of the transistor provided on the one electric current path and that of the transistor provided on the other electric current path are connected to drain electrodes of the counterparts. According to the construction, the amplitude of an input signal can be made smaller than a supply voltage of the logical circuit.

Latch circuit, shift register circuit, logical circuit and image display device operated with a low consumption of power

A display device includes: a plurality of signal lines which extend in a zigzag manner in a column direction and to which image signals are supplied, respectively; an insulation film which covers the plurality of signal lines; and a plurality of pixel electrodes which are formed on the insulation film and to which the image signals are input from the plurality of signal lines, respectively. A distance between ones of the pixel electrodes located adjacent to each other in the column direction is equal to or larger than a line width of the signal lines.

Display device having particular signal lines

A display device includes a source line for supplying a display signal, a display pixel electrode, and a TFT for switching an electrical connection between the source line and the pixel electrode. The TFT includes a source electrode electrically connected to the source line, a drain electrode electrically connected to the pixel electrode, and a gate electrode for controlling an electrical connection between the source electrode and the drain electrode. A first auxiliary capacitor electrode and a second auxiliary capacitor electrode are connected to the drain electrode and respective connection portions between the drain electrode and the auxiliary capacitor electrodes are formed of a semiconductor material.

Display device and method for fabricating the same

A display device of the present invention comprises: a source line; a pixel electrode; a first TFT for switching an electrical connection between the source line and the pixel electrode; and a second TFT as a spare. The second TFT includes a semiconductor film and a gate electrode. The semiconductor film includes a source electrode and a drain electrode. The gate electrode is provided on the semiconductor film with a gate insulation film interposed therebetween. The display device includes an interlayer insulation film between the source line and the semiconductor film of the second TFT. The interlayer insulation film is thicker than the gate insulation film. When the first TFT is unusable, a contact hole is formed in the interlayer insulation film such that the source line is electrically connected to the source electrode, whereby the electrical connection between the source line and the pixel electrode is rendered switchable by the second TFT.

Electronic device, display device and production method thereof

If a clock signal ck is &ldquo;H&rdquo; and an input pulse signal in (first control signal) is &ldquo;H&rdquo;, then n-type transistors M and M are turned on to make an output node/OUT have the GND level. Then, a p-type transistor M is turned on to make an output node OUT have a Vcc (16 V) level. Thus, a latch circuit LAT operates as a level shifter circuit when first and second control signals and the clock signal ck are at &ldquo;H&rdquo; and operates as a level hold circuit in any other case. Therefore, the shift register circuit constructed of the latch circuit LAT functions as a low-voltage interface, and the input of the clock signal ck is stopped when the latch circuit LAT is inactive, so that the load and the consumption of power of the clock signal line are reduced.

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Tenri, Japan

Ichiro Shiraki