Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Ichiro Okabayashi

Yasuhiro Mori

Manabu Migita

Hiroshi Kadota

Shinji Furuya

Tetsuji Kishi

Masaki Yamauchi

Akihiro Kawabata

Katsuyuki Kaneko

Tadashi Okamoto

Yuri Kuwata

Shinji Sasaki

Jiro Miyake

Reiji Segawa

Junji Nishikawa

Yoshinori Maeda

A short film generation/reproduction apparatus for generating video of a short film using at least one still picture and reproducing such video is comprised of: a picture feature extraction unitfor extracting picture features from an input picture; a picture-to-style feature conversion unitfor converting the picture features into style features; a picture-to-musical feature conversion unitfor converting the picture features into musical features; a style determination unitfor determining a style based on the style features; a music determination unitfor determining a piece of music based on the musical features; and a scenario generation unitfor generating a scenario by using the still picture, music and style.

Short film generation/reproduction apparatus and method thereof

A still image producing apparatus in which a user selects one piece of information, and production of still images and music associated with the mood in time of the production is provided. A still image producing apparatuscomprises: an image feature extraction unitwhich analyzes image data, so as to extract feature; a music feature extraction unitwhich extracts a music feature quantity from music data; and a mapping process unitwhich uses each feature, so as to respectively map image data and music data on each sensitivity map using two axes. The user selects, from the sensitivity map, via a menu input unit, a quadrant for music or images desired in a slide show. Thus, the slide show associated with the mood is automatically produced in a slide show generation unit

Still image producing apparatus

An image display apparatus includes: a display displaying an image with a predetermined number of pixels; an image holding unit holding an original image composed of a number of pixels larger than a number of pixels that is displayable on the display; and an object judgment unit judging whether or not an object is included in the original image held in the image holding unit, and generating object information related to the object in a case where the object is included in the original image. The image display apparatus also includes a display image generation unit extracting at least a part of an object area from the original image based on the original image specified by the user as well as on the object information corresponding to the original image, and generating a display image composed of a number of pixels corresponding to the number of pixels that is displayable on the display.

Image display apparatus

A data processing control system has a controller wherein the controller (1) sends every received instruction to the plurality of data processing devices until the number of instructions being executed or waiting to be executed by the plurality of data processing devices reaches a predetermined number, (2) does not send any received instructions to the plurality of data processing devices but holds the received instructions in a queue once the number of instructions being executed or waiting to be executed by the plurality of data processing devices has reached the predetermined number, and (3) when the number of instructions being executed or waiting to be executed by the plurality of data processing devices has become zero by completing the execution thereof, starts sending the queued instructions in sequence to the plurality of data processing devices, and continues to send the queued instructions or every newly received instruction to the plurality of data processing devices until the number of instructions being executed or waiting to be executed by the plurality of data processing devices reaches the predetermined number.

Data processing control system, controller, data processing control method, program, and medium

An ultrasonic tomography apparatus has an ultrasonic transmitter for transmitting an ultrasound to an object body; an ultrasonic receiver for receiving ultrasound reflected from an object body and producing an ultrasonic signal; a filter for extracting components of the ultrasonic signal in at least two different frequency bands; and an image generator for generating an ultrasonic tomogram of the object body based on the extracted ultrasonic signal component in a first frequency band and the extracted ultrasonic signal component in one or more second frequency bands. The first frequency band centers on a frequency band at the time of transmission, and the second frequency band is shifted from the frequency band at the time of transmission.

Ultrasonic tomography apparatus and ultrasonic tomography method

The data storage array apparatus having a RAID configuration according to the present invention comprises an internal access issuance part which issues internal access requests to data storage parts a group response monitoring part which monitors processing responses in the data storage parts until an internal access requesting group satisfies a predetermined condition and issues a notice of completion of monitoring, an external access response part which notifies to outside of completion of external access in response to a predetermined situation, a continuous response monitoring part which further continuously monitors, based on the notice of completion of monitoring, processing responses for each HDD with respect to an internal access request which was met with no processing response from the data storage parts, and an array operation control part which controls, based on continuous response monitoring information from the continuous response monitoring part, issuance of internal accesses to the respective data storage parts.

Data storage array apparatus, method of controlling access to data storage array apparatus, and program and medium for data storage array apparatus

A data readout time adjuster to be used for a video-on-demand system includes the following units. A readout time adjusting data storage unit stores image data for adjusting readout time to be provided to subscribers who have not been assigned the readout right and are waiting for a start of a readout operation. The image data for adjusting readout time cause no inconvenience even if a transmission of the image data is interrupted any time. A readout start position check unit checks an expected time of an occurrence of the readout right and a readout start position at the expected time in response to an additional data transmission request. A readout control unit makes at least one of the readout unit and a private readout unit exclusively provided or the readout time adjusting data storage unit read the image data for adjusting readout time stored in the readout time adjusting data storage unit until the time of the occurrence of the readout right, for the subscribers who have checked the expected time and the readout start position. A readout time adjusting data transmission control unit controls the transmission unit to transmit the image data for adjusting readout time read by the readout control unit to the subscribers who are waiting for the readout right until the time of the occurrence of the readout right.

Image data readout time adjuster for a video-on-demand system

A data transfer apparatus for providing efficient data transfer between one memory device and multiple devices by providing high speed switching of the multiple devices according to a count of the number of the data transfers performed between the one memory device and any of the multiple devices. The data transfer apparatus comprises a transferring unit for controlling a data transfer between the memory and a device; a counting unit for counting one each time data is transferred; and a selecting unit for selecting a device in accordance with a count value by decoding the count value output from the counting unit. The transferring unit controls the data transfer between the memory and the device selected by the selecting unit. The above data transfer apparatus may include the counting unit consisting of n-bits of a binary counter, 2.sup.n devices, and the selecting unit consisting of a decoder that inputs n-bits and outputs 2.sup.n -bits of data.

Data transfer apparatus and system providing high speed switching to

Image and sound data stored in an optical disc unit having an medium auto-changer mechanism are read out and temporarily stored in a hard disk unit, after then supplied to a user's terminal unit via a memory which serves as an output buffer. The image and sound data are stored in the memory, by compressing and a time length required to read out the data is shorter than a reproduction time in the user's terminal unit, and therefore plural data are read out by a difference between a readout time and the reproduction time. Since write operation to the hard disk unit and readout operation from the hard disk unit to write to the main memory 3 are simultaneously carried out, plural hard disk units are disposed and accessed in parallel. Moreover, a unit of data in write operation is larger than a unit of data in readout operation in the hard disk unit.

Video server apparatus comprising optical disks, hard disk drive and

In a system for executing distribution, arrangement and collection of array data between a host processor and plural processor elements, control parameter regarding array data to be transferred and an identification number assigned to each data receiver are set beforehand to a data receiver of each processor element. Data sequentially sent out onto a data bus with synchronization with a strobe signal from the data transmitter of the host processor are fetched selectively according to a data transfer allowance signal generated based on the control parameter and the identification number. The fetched data is written into a memory with a discrete address.

Data transfer device and multiprocessor system

One data transmitter for transmitting a broadcast data onto an outside data bus and data receivers, whose number is 'n', for individually receiving the transmitted broadcast data are provided. A single error signal line is connected in common to the data transmitter and each of the 'n' data receivers. Each of the data receivers notifies an error detection to the data transmitter and the other data receivers via the error signal line with a wired OR connector when its own data receivers detects an error. Being notified of the error detection, the data transmitter re-transmits the data so that all of the data receivers re-receive the data. Accordingly, re-transfer per one data at a broadcast transfer is contemplated.

High speed data transfer device having improved efficiency

A parallel processing system consists of a plurality of processor elements and a network for connecting the processor elements to each other. The processor includes a processor, a memory and a data transfer apparatus, all connected to a common bus. The data transfer apparatus includes of three buffers, while a data relay includes two buffers. In data transfer from a processor element to another processor element, a data is relayed in a third processor element only with use of a buffer, or a write/read operation is not performed in the third processor element. Then, the overhead is decreased and the transfer capability is improved. Further, the data transfer apparatus does not access the common bus, so that the width of the bus can be increased, and the processing performance of the processor can be improved.

Parallel processing system and data transfer method which reduces bus

There are provided a data transmitter for sequentially transmitting data to which error correcting codes are added, and a data receiver for returning a retransmission request signal if the received data has errors which cannot be corrected. The data transmitter does not confirm that the retransmission request signal related to the transmitted data is received and data are consecutively transmitted from a FIFO memory in a pipeline fashion while holding the transmitted data in a data latch. The data receiver sequentially stores the received data in the FIFO memory on a receiving end in a pipeline fashion. In the case where the retransmission request signal is transmitted from the data receiver, the data transmitter immediately transmits retransmission data which has been prepared in the data latch.

Data transfer device

In a memory access device, each of read and write addresses generated by read and write address generating means is stored in a read or write address buffer through a read or write address latch. The memory is accessed based on an address supplied by either address buffer from the bottom side thereof. Each address generating means is arranged such that, when a generated address is stored in the corresponding address buffer, the address calculation stage is finished. Exception detecting means is arranged to conduct exception detection on each address before the address is supplied from the corresponding address buffer, i.e., while the address is being latched by the corresponding address latch. Accordingly, the exception detection on each address can be conducted independently from a pipeline operation, thus shortening the execution time of each calculation stage. This prevents the calculation stage from forming a critical path.

Memory access device

At data transfer, a processor sends an address to an address bus and sends a data to a data bus. In a transfer control unit, a comparator compares an outside address signal inputted via the address bus with an inside address signal generated in an address generating part. When the signals coincide with each other, the comparator outputs a coincidence signal. Receiving the coincidence signal, a control part sends a write signal to a buffer and a data on the data bus is stored in the buffer. The address generating part proceeds to a next address according to the write signal. The data in the buffer is sent outside from a port thereafter. Thus, a program for high-speed data transfer is easily programmed with an ordinary code of a processor for general purpose.

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Osaka, Japan

Ichiro Okabayashi