Nec Corporation

Other

Nec Corporatoin

Ichiro Kondo

Nobuyuki Tanaka

Hiroyuki Kobatake

Shigeo Nomura

Kouji Yamaoka

Seijiyu Kawamata

Mamoru Kasahara

The object of the invention is to provide a water immersion detecting circuit, which is free from false detection and is stable and highly sensitive in operation. There is provide a water immersion detecting circuit provided on a printed board of an electronic unit and used for detecting water immersion of the electronic unit based on a change of resistance generated between a pair of sensor electrodes for detecting water immersion P , p , wherein the pair of sensor electrodes P , P are positioned opposite to each other on the printed board , and a U-shaped slit (opening) is formed between the sensor electrodes P , P

Water immersion detecting circuit

The present invention provides a semiconductor device with small space factor, which controls the application of voltages higher than a power supply voltage to internal circuits. This device includes a first transistor provided with a semiconductor substrate of one conductive type, a first region of second conductivity type formed in the semiconductor substrate, a second region of the second conductivity type formed independent of the first region, a third region of the first conductivity type formed in the first region, and a fourth region of the first conductivity type formed in the first region independent of the third region, having the first region as its back gate, and a second transistor provided with a fifth region of the first conductivity type formed in the second region and a sixth region of the first conductivity type formed in the second region independent of the fifth region, having the second region as its back gate, wherein a back gate bias voltage higher than the power supply voltage applied to the second region is applied to the first region.

Semiconductor device having device supplying voltage higher than power

In order to shorten initialization time, a flash type non-volatile semiconductor memory of the invention comprises a line decoder (2) for selecting all of word lines (WL1 to WLm), a word line voltage generator (3) for generating various voltage, a column decoder (4) for selecting or not selecting all of digit lines (DL1 to DLn). Erase pulse impression process is performed by supplying a positive first word line voltage to all the word lines (WL1 to WLm) selected, and an erase voltage (Vs) to a source line, leaving all the digit line floating. All of memory-cell-transistors (MC11 to MCmn) are erased by infusing hot carriers in their floating gates by way of avalanche breakdown caused between their sources and substrates. Depression discrimination is performed with a sense amplifier (8) by selecting all digit lines (DL1 to DLn) and supplying all word lines (WL1 to WLm) with a second word line voltage.

Non-volatile semiconductor memory

A direct current booster device has a booster which includes a plurality of N-channel MOS field-effect transistors (FETs) each having a gate terminal and a drain terminal joined together and connected in series in the same direction from the input side to the output side, and a plurality of capacitors to which two boosting clock signals of an opposite phase are provided, which are generated by a clock driver circuit and supplied alternately in a one-by-one corresponding relationship so that the two different boosting clock signals are inputted to each pair of adjacent gate-drain terminals of the FETs. A test circuit is provided, which has a plurality of N-channel MOS FETs, the source terminals of which are connected individually to the gate terminals of the FETs of the booster. The drain terminals of the MOS FETs of the test circuit are all connected in common to a test voltage supply terminal of the input unit for a testing voltage which is higher than a maximum voltage generated by the booster and applied to the capacitors. The gate terminals of the MOS FETs of the test circuit are all connected in common to a control signal terminal of a switching unit to which a control signal of a voltage up to the test voltage is supplied.

Direct current booster with test circuit

An electrically programmable read only memory device in a read-out mode of operation lifts one of the word lines to a read-out voltage level higher than an external power voltage level to see whether or not a designated floating gate type memory transistor provides a conductive channel, and the selected word line is firstly lifted to a first predetermined voltage level with a power voltage line, then being further lifted to the read-out voltage level supplied from a step-up circuit, wherein a monitoring unit is provided for the word lines for detecting the first predetermined voltage level so that an address set-up period is minimized without margin for fluctuation of process parameters.

Electrically programmable read only memory device with timing detector

In an oscillation circuit, the Schmidt circuit generates the control signal of the first level when the charge-discharge voltage inputted from the capacitor shifts to a voltage higher than the first threshold voltage and generates the control signal of the second level when the charge-discharge voltage shifts to a level lower than the second threshold voltage. The switching circuit connects the second current source circuit with the capacitor when the control signal is of the first level and connects the first current source circuit with the capacitor when the control signal is of the second level.

Oscillation circuit operating with stable oscillation frequency at a

A test circuit is incorporated in a semiconductor memory device including at least one ultraviolet erasable and electrically programmable non-volatile memory cell having a control gate and a floating gate. The test circuit comprises a switching circuit for selectively supplying the control gate of the memory cell with a voltage which is higher than a power supply voltage for ordinary reading a content of the memory cell, through a write voltage supply line used for writing data to the memory cell. The switching circuit makes it possible to test the written state of the memory cell with a voltage different from the normal reading power supply voltage.

Growing community of inventors

Tokyo, Japan

Ichiro Kondo