Tokyo Shibaura Denki Kabushiki Kaisha

Kabushiki Kaisha Toshiba

Fujitsu Corporation

Ichiro Kobayashi

Yoshiaki Moriya

Yukio Kitagawa

Hiroshi Iwahashi

Masamichi Asano

Yasoji Suzuki

Isao Abe

Eishin Yamakawa

Osamu Matsumoto

Kazuyoshi Shinada

Tadashi Maruyama

Tomohisa Shigematsu

Hiroyoshi Murata

Yoshihisa Shiotari

Yoshihiro Mitobe

Tuneo Nishi

Takuya Tomoi

In the method of the present invention, lubricant layers of magnetic discs, which have fixed thickness, can be formed by volatilizing solvent. The method of forming the lubricant layer on the magnetic disc, comprises the steps of: dipping the magnetic disc into a solution in which the lubricant is diluted with the volatile solvent; taking out the magnetic disc from the solution; and volatilizing the volatile solvent from a surface of the magnetic disc, wherein a layer of specific liquid, whose specific gravity is less than that of the solution and which is less volatile and insoluble in the solution, is formed on a surface of the solution.

Method of forming lubricant layer on magnetic disc, device for forming

A memory cell of a nonvolatile semiconductor memory device includes a P conductive type semiconductor substrate, first and second diffusion layers of an N conductivity type, formed in the substrate, a channel region formed in the surface region of the substrate, and which is located between the first and second diffusion layers, a floating gate electrode formed on the channel region, and a control gate electrode formed on the floating gate electrode. The memory cell further includes a third diffusion layer of the N conductivity type, and formed between the first layer and the channel region, the third layer having an impurity concentration lower than that of the first layer.

Nonvolatile semiconductor memory device with a double gate structure

An integrated circuit having a multi-layer interconnection structure comprises a logic section of series-connected MOS FETs each having a gate input connection layer made of a polysilicon layer on a semiconductor substrate of one conductivity type and source and drain semiconductor regions of the other conductivity type formed in the surface of the substrate along such a direction as to traverse the gate input connection layer, a load device connected to one end of the logic section, and interconnection structure for causing a signal, at a junction of the load device and logic the section, to be transmitted to the other end of the logic section across the gate input connection layer.

Integrated circuit having a multi-layer interconnection structure

A protected MOS transistor circuit includes an input MOS transistor and a depletion mode MOS transistor having a drain-source current path connected between ground and the gate of the input MOS transistor of obviating rupture of the gate oxide of the input MOS transistor when power is off. The depletion mode MOS transistor's gate receives a control signal only when power is on which renders the depletion mode MOS transistor nonconductive when power is on. The depletion mode MOS transistor is conductive when power is off.

Circuit including an MOS transistor whose gate is protected from oxide

In a data processing apparatus including an instruction register and an instruction decoder connected therewith, when a designation instruction (operand changing instruction) is set in the instruction register, the operand (the code of source or destination) of the designation instruction is registered in a source address register or a designation address register connected to the instruction register through a gate circuit. The registers produce control signals through decoders respectively for selecting predetermined operands. When the designation instruction is decoded by the instruction decoder a first (for source) and a second (for destination) flip-flop circuits which are connected to the output terminal of the instruction decoder are set. The outputs of these flip-flop circuits are applied to the negative input of an AND gate circuit connected to the instruction decoder. When an instruction to be executed subsequent to the designation instruction is decoded by the instruction decoder, the instruction decoder produces a control signal that selects the operand of the instruction, but this control signal is selectively blocked by the AND gate circuit, with the result that the operand designated by the designation instruction is substituted by the operand of the instruction to be executed subsequently.

Data processing apparatus

A memory address designating system comprising a program counter and data counter for holding the addresses of an instruction word area and data area respectively of a memory, an increment/decrement counter for modifying the address, and gate circuits for controlling data transfer between the program counter, data counter and increment/decrement counter, in which, when the memory is accessed by the addresses of the instruction word area and data area of the memory, an address held in the program counter is modified by an increment/decrement counter and consequently is incremented by one and sent through a gate to the data counter where it is held. On the other hand, the address of the data area held in the data counter is supplied through a gate to he program counter and then to the increment/decrement counter where it is modified. At the same time, the data of the data area of the memory is fetched and the modified address is supplied to the data counter while the modified address stored in the data counter is supplied to the program counter.

Memory address designating system

Two flip-flops for carry information are provided in a data processor; one for carry of arithmetic operation and the other for carry occuring when a program counter is incremented. A state of the latter flip-flop provides a condition of a conditional branch instruction. With the provision of those flip-flops, a multidigit operation can be performed without increasing programsteps to save carry information attendant on the operation data. A simple program may be prepared without increasing hardware for skip instruction processing.

Growing community of inventors

Kawasaki, Japan

Ichiro Kobayashi