Kabushiki Kaisha Toshiba

Ichiro Ishihara

Naoki Itoh

Toshio Kanai

Masahide Aoyama

An analog multiplexer circuit comprising bipolar differential amplifying input circuits, an active load circuit, a selector circuit, an emitter-grounded circuit, and a switch circuit. Differential analog signals are supplied to each of the input circuits. The active load circuit functions commonly for the input circuits. The selector circuit selects one of the input circuits in accordance with a selection signal. The emitter-grounded circuit is used to output the differentially amplified signal generated by the differential amplifying circuit constituted by the selected input circuit and the active load circuit. The switch circuit is inserted between the active load circuit and one of the input circuits and is turned on and off by the selection signal. When the one of the input circuits is not selected, the switch circuit is off, thus electrically disconnecting the one of the input circuit from other input circuit. When the one of the input circuits is selected, the switch circuit is on, thus electrically connecting the one of the input circuit and the active load circuit.

Analog multiplexer circuit having an active load circuit functioning

A differential amplifier pair includes first and second transistors emitters of which are connected to each other. A first current source is connected to a common emitter connection point of the first and second transistors. A source of a first MOS transistor is connected to a collector of the first transistor, and a source of a second MOS transistor is connected to a collector of the second transistor. Drains of the first and second MOS transistors are commonly connected to each other, and a second current source is connected to a common drain connection point. The first and second MOS transistors are selectively controlled to be turned on in accordance with an output from the differential amplifier pair.

Schmitt voltage comparator

Disclosed is a differential amplifier circuit which includes a first NPN transistor, a second NPN transistor, a current source connected to the emitters of the first and second NPN transistors, a first PNP load transistor having a collector connected to the collector of the first NPN transistor, a second PNP load transistor having a collector coupled to the collector of the second NPN transistor, and an FET having a gate connected to the collector of the first NPN transistor, and a source connected to the bases of the first and second PNP load transistors. A DC input current of the FET is substantially zero, and is designed to absorb a current corresponding to the gate potential of the FET, from the bases of the first and second PNP load transistors.

Differential amplifier circuit

A comparison circuit includes a differential amplifier having first and second input circuits each of which is formed of darlington-connected transistors and which are connected to receive first and second input signals. The comparison circuit further includes an operation mode control circuit for selectively short-circuiting the base-emitter path of each of the first stage bipolar transistors in the first and second input circuits, in response to the first and second input signals.

Growing community of inventors

Tokyo, Japan

Ichiro Ishihara