Nec Corporation

Ichiro Hirai

Toru Amano

Tsuyoshi Abe

Shinichiro Iwata

Kazuhiro Kawamoto

Jun Morizono

A hub apparatus comprises a first port that receives predetermined cascade-supplied differential signals; a plurality of second ports that receive and output the predetermined differential signals; a third port that cascade-outputs the predetermined differential signals; a plurality of differential signal line pairs that daisy-chain connect the first port, the plurality of second ports, and the third port in this order from upstream to downstream; and a terminator provided between two differential signal lines that constitute a differential signal line pair connecting the last-stage second port out of the plurality of second ports to the third port.

Hub apparatus and control system

A buffer memory circuit has a memory circuit for receiving input data possessing a transmission rate selected out of a plurality of predetermined transmission rates, a write-in clock signal synchronized with these input data and a read-out clock signal having a predetermined rate. The memory circuit stores the input data according to the write-in clock signal, and supplies the input data, which have been stored, as output data according to the read-out clock signal. A detecting circuit detects an overflow or an underflow in the memory circuit, and supplies a resetting pulse signal for initializing the memory circuit. A control circuit receives the write-in clock signal and the resetting pulse, and suspends the supply of the read-out clock signal to the memory circuit means for a certain period of time, determined by the first transfer rate, from the time of receiving the resetting pulse signal.

Buffer memory circuit having constant propagation delay

A phase-adjusting circuit for adjusting the phase relation between an input data string supplied via input lines includes sync detecting apparatus provided for each of the lines for generating frame sync-detection signals by detecting frame sync signals of the input data strings. Apparatus is provided for detecting a first data string having a largest delay of the input data strings. A phase difference-detecting apparatus detects phase differences between the first and the remaining data strings to produce phase difference signals for such remaining data strings. A line connecting signal-generating apparatus is responsive to the phase difference signal for generating line connecting signals. A variable-delay apparatus is responsive to the phase difference signals for outputting delayed data strings by giving delays to the remaining data strings. A first switching apparatus responsive to the line connecting signals delivers the remaining data strings to the variable-delay apparatus and outputs the first data string in an undelayed state. A second switching apparatus responsive to the line connecting signals delivers the first data string and the delayed data strings to output lines corresponding to the input lines.

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Tokyo, Japan

Ichiro Hirai