Hitachi, Ltd.

Renesas Technology Corp.

Other

Texas Instruments Corporation

Hitachi Microcomputer System, Ltd.

Hitachi Cable, Inc.

Hitachi Ulsi Systems Co., Ltd.

Akita Electronics Systems Co., Ltd.

Ichiro Anjoh

Asao Nishimura

Kunihiko Nishi

Kunihiro Tsubosaki

Makoto Kitano

Akio Hasebe

Akihiro Yaguchi

Gen Murakami

Hiroyoshi Kokaku

Chuichi Miyazaki

Hideki Tanaka

Masahiro Ichitani

Junichi Saeki

Shuji Eguchi

Masanori Segawa

Ryosuke Kimoto

Akira Nagai

Isamu Yoshida

Yukiharu Akiyama

Tomoaki Kudaishi

Masahiko Ogino

Masatsugu Ogata

Masanori Shibamoto

Hiroshi Kikuchi

Takashi Yokoyama

Takashi Yamazaki

Hiroshi Hozoji

Kazuyoshi Oshima

Aizo Kaneda

Shozo Nakamura

Sueo Kawai

Noriyuki Kinjo

Syuuji Eguchi

Tetsurou Matsumoto

Junichi Arita

Naotaka Tanaka

Mamoru Mita

Nae Yoneda

Ryuji Kohno

Toshiaki Ishii

Takumi Ueno

Masamichi Ishihara

Nobutake Tsuyuno

Shigeharu Tsunoda

Akihiko Iwaya

Norio Okabe

Toshiya Satoh

Michael A Lamson

Katherine G Heinen

Tetsuo Kumazawa

Michiharu Honda

Kenichi Otsuka

Kazuya Ooji

Kazunari Suzuki

Makoto Morishima

Michio Tanimoto

Rie Hattori

Taisei Jin

Shunji Koike

Toshiak Ishii

Haruo Akahoshi

Hiroshi Satoh

Yasunori Yamaguchi

Masazumi Amagai

Darvin R Edwards

Toshiyuki Sakuta

Yasuhiro Kasama

Ryo Haruta

Eiji Miyamoto

Kazuya Ito

Tetsu Udagawa

Mitsuaki Haneda

Satoshi Oguchi

Tadanori Segawa

Takeshi Terasaki

Lim T Beng

Syuji Eguchi

Ryo Moteki

Masnori Shibamoto

Youichi Matsuno

Atsusi Nozoe

Chai T Chong

Hiroyuki Ohta

Kenichi Yamamoto

Tetsuro Matsumoto

Hideo Arima

Hiroshi Koyama

Kazuhiro Sugino

Toshihiro Yasuhara

Takehiro Ohnishi

Noriou Shimada

Maya Obata

Kenichi Imura

A semiconductor device includes a semiconductor chip formed with connection terminals, an elastic structure interposed between a main surface of the chip and a wiring substrate formed with wirings connected at first ends thereof to the connection terminals, and bump electrodes connected to the other ends of the wirings. The connection terminals may be at a center part or in peripheral part(s) of the chip main surface and both the elastic structure and wiring substrate are not provided at locations of connection terminals. A resin body seals at least the connection terminals and the exposed first ends of wirings (leads). In a scheme in which the connection terminals are located in a peripheral part of the chip main surface, the wiring substrate protrudes beyond the chip boundary where the connection terminals are arranged, and the resin body shape is restricted by the protruding part of the wiring substrate.

Semiconductor device and manufacturing method thereof

Semiconductor devices,-semiconductor wafers, and semiconductor modules are provided: wherein the semiconductor device has a small warp; damages at chip edge and cracks in a dropping test are scarcely generated; and the semiconductor device is superior in mounting reliability and mass producibility. The semiconductor devicecomprising: a semiconductor chipa porous stress relaxing layerprovided on the plane, whereon circuits and electrodes are formed, of the semiconductor chip; a circuit layerprovided on the stress relaxing layer and connected to the electrodes; and external terminalsprovided on the circuit layer; wherein an organic protecting filmis formed on the plane, opposite to the stress relaxing layer, of the semiconductor chip, and respective side planes of the stress relaxing layer, the semiconductor chipand the protecting filmare exposed outside on a same plane.

Semiconductor device, semiconductor wafer, semiconductor module, and a method of manufacturing semiconductor device

A semiconductor device having a superior connection reliability is obtained by providing a buffer body for absorbing the difference of thermal expansion between the mounting substrate and the semiconductor element in a semiconductor package structure, even if an organic material is used for the mounting substrate. A film material is used as the body for buffering the thermal stress generated by the difference in thermal expansion between the mounting substrate and the semiconductor element. The film material has modulus of elasticity of at least 1 MPa in the reflow temperature range (200&#x2013;250&#xb0; C.).

Circuit tape having adhesive film semiconductor device and a method for manufacturing the same

In a semiconductor device having a three-layered buffer layer comprising core layerhaving interconnected foams such as a three-dimensional reticular structure and adhesive layersprovided on both sides of the core layer as a stress buffer layer between semiconductor chipand wiringto lessen a thermal stress generated between the semiconductor device and the package substrate, where a thickness ratio of the core layerto total buffer layer is at least 0.2, the production process can be simplified by using such a buffer layer, thereby improving the mass production capacity and enhancing the package reliability.

Wiring tape for semiconductor device including a buffer layer having interconnected foams

Semiconductor devices, semiconductor wafers, and semiconductor modules are provided, wherein: the semiconductor device has a small warp; damage at the chip edge and cracks occurring in a dropping test are scarcely generated; and the semiconductor device is superior in mounting reliability and mass producibility. The semiconductor includes a semiconductor chip; a porous stress relaxing layerprovided on the plane, whereon circuits and electrodes are formed, of the semiconductor chip; a circuit layerprovided on the stress relaxing layer and connected to the electrodes; and external terminalsprovided on the circuit layer; wherein an organic protecting filmis formed on the plane, opposite to the stress relaxing layer, of the semiconductor chip, and respective side planes of the stress relaxing layer, the semiconductor chip, and the protecting filmare exposed outside on the same plane.

A semiconductor plastic package, more particularly a preferred package structure and method for making a BGA package. A resin sealed BGA package where a supporting frame which fixedly supports semiconductor parts; i.e., an IC chip, a circuit board, or a circuit film, is sealed with resin, using a mold which is composed of an upper mold half and a lower mold half with the lower mold half having a plurality of projections, one at a position corresponding to each of the external terminals. The mold has a divisional structure which has an air vent between the divisional elements thereof.

Semiconductor devices and methods of making the devices

A semiconductor device which can improve the connection reliability of solder bumps and productivity in manufacturing. Insulating tape having wiring patterns on its surface is bonded to a lead frame. Semiconductor elements are loaded and circuit formed surfaces and sides of the semiconductor elements are sealed with sealing resin. After arrangements of individual semiconductor devices are formed, the lead frame is separated into individual metal plates to form individual semiconductor devices. Such simultaneous production of a plurality of semiconductor devices enhances productivity, and improves flatness of the insulating tape, whereby the connection reliability of solder bumps is improved.

Semiconductor device and lead frame therefor

A semiconductor device having a superior connection reliability is obtained by providing a buffer body for absorbing the difference of thermal expansion between the mounting substrate and the semiconductor element in a semiconductor package structure, even if an organic material is used for mounting substrate. A film material is used as the body for buffering the thermal stress generated by the difference in thermal expansion between the mounting substrate and the semiconductor element. The film material has modulus of elasticity of at least 1 MPa in the reflow temperature range (200-250&deg; C.).

Circuit tape having adhesive film, semiconductor device, and a method for manufacturing the same

A semiconductor device and a manufacturing method thereof, which device includes a semiconductor element arranged to form integrated circuitry, a plurality of electrode pads formed on the side of the integrated circuitry formation surface of the semiconductor element, bump electrodes for electrically connecting to the electrode pads through a conductive layer, and a stress relaxation layer formed between the integrated circuitry formation surface and electrode pads on one hand and the bump electrodes and conductive layer on the other hand, the stress relaxation layer being adhered thereto, wherein more than one third of the stress relaxation layer from a surface thereof is cut away for removal and wherein the stress relaxation layer is subdivided into a plurality of regions. Accordingly, it is possible to provide a semiconductor device capable of offering high density mounting schemes with increased reliability while reducing production costs.

Semiconductor device comprising stress relaxation layers and method for manufacturing the same

Electrode pads are formed on a tape circuit to correspond to positions of solder bumps on an IC. A plurality of pins formed on a periphery of the tape circuit provide electrical connection between the tape circuit and a mother socket. An elastomer sheet is provided between a portion of the tape circuit, on which the electrode pads are formed and the IC is mounted, and the mother socket, and a side surface of the sheet, which contacts with the tape circuit, is formed with cut grooves in lattice fashion such that respective centers of the electrode pads substantially coincide with intersections of the grooves. Thus portions defined by the grooves on the sheet are made independent from one another to enable accommodating pushing forces from the solder bumps, so that, even if dispersion in height generates between the solder bumps, the respective portions defined by the grooves are hardly influenced by one another, and so accommodate the pushing forces from the solder bumps to permit the solder bumps and the electrode pads to surely contact with each other.

Socket for testing of semiconductor device, and semiconductor device and method of manufacturing the semiconductor device

A semiconductor plastic package, more particularly a preferred package structure and method for making a BGA package. A resin sealed BGA package where a supporting frame which fixedly supports semiconductor parts; i.e., an IC chip, a circuit board, or a circuit film, is sealed with resin, using a mold, which is composed of an upper mold half and a lower mold half with the lower mold half having a plurality of projections, one at a position corresponding to each of the external terminals. The mold has a divisional structure which has an air vent between the divisional elements thereof.

Method of manufacturing a semiconductor device a ball grid array package structure using a supporting frame

A ball grid array type semiconductor package includes a semiconductor chip formed with bonding pads, an elastomer bonded to the semiconductor chip, a flexible wiring substrate bonded to the elastomer and formed with wirings connected at one end of the bonding pads of the semiconductor chip, a solder resist formed on the main surface of the flexible wiring substrate and solder bump electrodes connected to the other ends of the wirings. The elastomer is bonded to the flexible wiring substrate on the side of the tape, the solder resist is formed on the side of the wirings, and the solder bump electrodes are connected with the wirings by way of through holes formed in the solder resist.

Method of manufacturing a ball grid array type semiconductor package

Growing community of inventors

Koganei, Japan

Ichiro Anjoh