Hitachi, Ltd.

Renesas Technology Corp.

Elpida Memory, Inc.

Other

Hitachi, Ltd., Intellectual Property Group

Ichiro Anjo

Asao Nishimura

Hiroshi Hozoji

Kunihiro Tsubosaki

Masahiro Ichitani

Akihiro Yaguchi

Hiroshi Kikuchi

Kunihiko Nishi

Takashi Yokoyama

Gen Murakami

Makoto Kitano

Akio Hasebe

Takashi Yamazaki

Kazuyoshi Oshima

Aizo Kaneda

Shozo Nakamura

Junichi Saeki

Isamu Yoshida

Sueo Kawai

Noriyuki Kinjo

Hiroyoshi Kokaku

Masatsugu Ogata

Masanori Segawa

Syuuji Eguchi

Tetsuro Matsumoto

Yoshihide Yamaguchi

Masahiko Ogino

Akira Nagai

Toshiya Satoh

Mitsuaki Katagiri

Hiroyuki Tenmei

Shuji Eguchi

Masanori Shibamoto

Naoya Kanda

Shigeharu Tsunoda

Kosuke Inoue

Noriyuki Oroku

Madoka Minagawa

Kenji Ujiie

Akira Yajima

Takumi Ueno

Toshio Miyamoto

Tadanori Segawa

Hideki Tanaka

Yuji Watanabe

Haruo Akahoshi

Chuichi Miyazaki

Hisashi Tanie

Yukiharu Akiyama

Ryo Haruta

Tomoaki Kudaishi

Junichi Arita

Hiroshi Koyama

Katsuyuki Matsumoto

Takehiro Ohnishi

Noriou Shimada

Takao Miwa

Atsushi Kazama

Yuji Shirai

Koji Hosokawa

Hiroaki Ikeda

Tomonori Sekiguchi

Hiroyuki Ohta

Masaharu Kubo

Hideki Osaka

Osamu Nagashima

Hiromi Abe

Tatemi Ido

Hitoshi Akamine

Tetsurou Matsumoto

Mitsuhisa Watanabe

Nae Hisano

Shuji Kikuchi

Katsunori Hirano

Osamu Kubo

Yuji Sonoda

A BGA semiconductor device includes a semiconductor package and a mounting board mounting thereon the semiconductor package, wherein an array of signal electrodes of the semiconductor package and an array of signal electrodes of the mounting board are coupled together via signal bumps. The BGA semiconductor device also includes a dummy bump, which reinforces the bending strength of the BGA semiconductor device and is broken by a shearing force caused by thermal expansion to alleviate the stress for the signal bumps.

BGA semiconductor device having a dummy bump

A semiconductor apparatus includes a semiconductor chip, a wired board, a plurality of bump electrodes, a plurality of external terminals, and insulating material. The semiconductor chip includes a plurality of electrode pads arranged in a central area on one surface. The wired board is arranged as facing one surface of the semiconductor chip, and includes a wiring. The bump electrode is provided between surfaces at which the semiconductor chip and the wired board face each other, and electrically connects the electrode pad and the wiring. The external terminal corresponds to a plurality of bump electrodes, and is mounted on the wired board. The insulating material is provided between the semiconductor chip and the wired board, and covers at least a connection part between the bump electrode and the wiring. The wiring of the wired board is configured to run in a straight line from a bump electrode-mounted position in a semiconductor chip-mounted surface of the wired board, to an external terminal-mounted surface of the wired board, and also, electrically connect the bump electrode and the corresponding external terminal.

Semiconductor package with reduced length interconnect and manufacturing method thereof

The present invention relates to a DRAM stacked packages, a DIMM, a method for testing them, and a semiconductor manufacturing method. According to the present invention, there is provided a DRAM stacked package comprising: a plurality of stacked DRAMs; external terminals to which test equipment is connected, said external terminals being used to input/output at least address, command, and data; and an interface chip provided between said plurality of stacked DRAMs and said external terminals. The plurality of DRAMs and the interface chip are implemented on a package. The interface chip comprises: a test circuit including: an algorithmic pattern generator for generating a test pattern used to test the plurality of DRAMs; applying circuits for applying said generated test pattern to the plurality of DRAMs; and a comparator for comparing each response signal received from the plurality of DRAMs with an expected value for judgment.

DRAM stacked package, DIMM, and semiconductor manufacturing method

A semiconductor storage employs a base substrate () having a command/address external terminal group (CA), a data input/output external terminal group (DQ), and a single chip select external terminal (CS), and also comprises a plurality of memory chips () to () mounted on a base substrate (), each of which can individually carry out read and write operations. The terminals (CA), (DQ), and (CS) are connected to an interface chip (). The interface chip () has a chip select signal generation circuit that can individually activate a plurality of memory chips () to () on the basis of an address signal fed by way of the terminal (CA) and on the basis of a chip select signal fed by way of the terminal (CS).

Semiconductor storage device having a plurality of stacked memory chips

The present invention is a semiconductor device having the semiconductor element obtained by cutting a semiconductor wafer with the electrode pad formed on one side along a scribe line, a semiconductor element protective layer on the semiconductor element which has a opening on the pad, a stress cushioning layer on the layer which has the opening on the pad, a lead wire portion reaching the layer from the electrode pad via the openings, external electrodes on the lead wire portion, and the conductor protective layer on the layers, the layer and the conductor protective layer forming the respective end faces on the end surface of the semiconductor element inside the scribe line and exposing the range from the end face of the end surface to the inside of the scribe line.

Semiconductor device and manufacturing method thereof

A semiconductor device capable of reducing a temperature increase during operation thereof is provided. In the semiconductor device, an interface chip is stacked on a plurality of stacked semiconductor elements. Both an 'Si' interposer and a resin interposer are arranged under the plural semiconductor elements. The Si interposer is arranged between the resin interposer and the plural semiconductor elements. The Si interposer owns a thickness which is thicker than a thickness of a semiconductor element, and also has a linear expansion coefficient which is smaller than a linear expansion coefficient of the resin interposer, and further, is larger than, or equal to linear expansion coefficients of the plural semiconductor elements.

Semiconductor device

A semiconductor apparatus in which flip chip bonding is enabled without any underfill, and which comprises a semiconductor device, an electrically insulating layer formed on the semiconductor device by mask-printing an electrically insulating material containing particles, and an external connection terminal formed on the electrically insulating layer and electrically connected with an electrode of the semiconductor device. The electrically insulating layer is formed with a thickness so as to provide &#x3b1;-ray shielding of the semiconductor device.

Semiconductor device and method for producing the same

CMOS logic LSI comprises, as a part thereof, n-channel MISFET's (Qn), p-channel MISFET's (Qp) and a first-layer wiring () to a third-layer () formed on a main surface of a silicon substrate (), and as another part, a fourth-layer wiring () to a seventh-layer wiring () formed on a main surface of a glass substrate () different from the silicon substrate (). The main surface of the silicon substrate () and the main surface of the glass substrate () are arranged in face-to-face relation with each other, and a plurality of microbumps (A) formed at the uppermost portion of the silicon substrate () and a plurality of microbumps (B) formed at the uppermost portion of the glass substrate () are electrically connected, thereby constituting the CMOS logic LSI as a whole.

Integrated circuit device having reduced substrate size and a method for manufacturing the same

Disclosed is a technique capable of enhancing the degree of freedom in the layout of a rerouting layer in a wafer level CSP in which defect repairing is performed by cutting a fuse. More specifically, after the defect repairing is performed by irradiating a laser beam to a fuse, an organic passivation layer (photo-sensitive polyimide layer) is filled in a fuse opening. Thereafter, a rerouting layer, a bump land, an uppermost wiring layer, and a solder bump are formed on the organic passivation layer. In the following steps of the defect repairing, the baking process to cure an elastomer layer and the uppermost protection layer is conducted at a temperature below 260&#xb0; C. in order to prevent the variance of the refresh times of memory cells.

Method of manufacturing a semiconductor integrated circuit device

A semiconductor integrated circuit device includes a semiconductor substrate, a circuit element formed on one major surface of the semiconductor substrate and constituting an integrated circuit having a plurality of functions or a plurality of characteristics, an internal connection terminal, connected to the integrated circuit, for selecting one of the plurality of functions or one of the characteristics in the integrated circuit, an insulating layer covering the internal connection terminal such that the internal connection terminal is selectively exposed, and an external connection terminal arranged on the insulating layer. One of the plurality of functions or one of the plurality of characteristics is selected by a connection state between the internal connection terminal and the external connection terminal.

Semiconductor device and manufacturing method of that

A semiconductor device having a semiconductor element is obtained by cutting a semiconductor wafer, having an electrode pad formed on one side thereof, along a scribe line. The semiconductor device has a semiconductor element protective layer on the semiconductor element so as to form an opening above the pad, a stress cushioning layer on the layer so as to form an opening on the pad, a lead wire portion reaching the layer from the electrode pad via the openings, external electrodes on the lead wire portion, and a conductor protective layer on the layer. The layer, the layer, and the conductor protective layer form respective end faces on the end surface of the semiconductor element inside the scribe line and expose a surface of the semiconductor element from the end face of the end surface to a point inside of the scribe line, thereby to expose the scribe line.

In a multi chip module of a structure wherein a plurality of bare or packaged semiconductor chips are mounted on a single wiring board and upper surfaces of the semiconductor chips are covered with a single heat spread plate, the whole space around the semiconductor chips thus sandwiched between the wiring board and the heat spread plate is filled with resin. By so doing, the semiconductor chips are interconnected through the resin, so that even if a stress is exerted on any of the chips, it is dispersed and therefore it is possible to diminish the occurrence of cracks in the chips and the heat spread plate caused by stress concentration. Besides, since the semiconductor chips and the heat spread plate are bonded together with resin, even if there are variations in size of the chips, both can be bonded easily. Further, the bonding of all the chips and the heat spread plate can be done in a single process.

Semiconductor module and mounting method for same

A semiconductor device is provided which enables a flip chip connection without use of underfill. The semiconductor device includes a semiconductor element having circuit electrodes and a circuit surface coated with a protecting film. A stress relaxation layer is provided by coating a cured thermoplastic resin onto the protecting film of the circuit surface in a manner which leaves the circuit electrodes exposed and curing it and having an inclination in the edge portion thereof. A wiring layer with wirings is connected to each of the circuit electrodes and disposed so as to make an electrical connection from the circuit electrodes, via the edge portion of the stress relaxation layer, and to a desired portion on the surface of the stress relaxation layer. A protecting film is provided thereon, and an external connection terminal is also provided.

Semiconductor device and method for manufacturing the same and semiconductor device-mounted structure

As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the 'Lead-On-Chip' or 'Chip-On-Lead' structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.

Growing community of inventors

Koganei, Japan

Ichiro Anjo