Hitachi, Ltd.

Renesas Technology Corp.

Renesas Electronics Corporation

Other

Hitachi Tohbu Semiconductor, Ltd.

Hitachi Tobu Semiconductor

Ichio Shimizu

Toshiyuki Hata

Nobuya Koike

Takeshi Otani

Asao Nishimura

Makoto Kitano

Akira Muto

Atsushi Nishikizawa

Kuniharu Muto

Jyunichi Tsuchiya

Hiroyuki Takahashi

Akihiro Yaguchi

Sueo Kawai

Yukihiro Satou

Katsuo Arai

Hiroshi Sato

Keiichi Okawa

Takuya Nakajo

Hidemasa Kagii

Katsuo Ishizaka

Akio Hoshi

Hiroyuki Nakamura

Masahiko Osaka

Hideo Miura

Gen Murakami

Yukihiro Sato

Kisho Ashida

Hiroi Oka

Norio Kido

Kenya Kawano

Tatsuhiro Seki

Sumio Okada

Kunihiko Nishi

Masachika Masuda

Takahiro Daikoku

Tadatoshi Danno

Naotaka Tanaka

Ryuji Kohno

Yuichi Machida

Munehisa Kishimoto

Tomio Yamada

Masayoshi Yoshimura

Soichiro Nakamura

Nae Yoneda

Nae Hisano

Keizo Otsuki

Kazuo Yamazaki

Toshio Hattori

Toshio Hatsuda

Toru Nagamine

Toshihiro Yasuhara

Toshinori Ozaki

Chikako Kitabayashi

Souji Sakata

Senji Shoji

Yuji Arai

Masahiro Saito

Akira Higuchi

Masanori Sakimoto

Tooru Nagamine

Tetsuo Iljima

Shigeru Ishii

The semiconductor device is high in both heat dissipating property and connection reliability in mounting. The semiconductor device includes a semiconductor chip, a resin sealing member for sealing the semiconductor chip, a first conductive member connected to a first electrode formed on a first main surface of the semiconductor chip, and a second conductive member connected to a second electrode formed on a second main surface opposite to the first main surface of the semiconductor chip, the first conductive member being exposed from a first main surface of the resin sealing member, and the second conductive member being exposed from a second main surface opposite to the first main surface of the resin sealing member and also from side faces of the resin sealing member.

Semiconductor device, a method of manufacturing the same and an electronic device

A semiconductor device is provided, which is capable of improving mounting flexibility relatively and increasing general versatility, as well as realizing heat radiation characteristics and low on-resistance. Moreover, the semiconductor device is provided, which is capable of improving reliability, performing processing in manufacturing processes easily and reducing manufacturing costs. Also, the semiconductor device capable of decreasing the mounting area is provided. A semiconductor chip in which an IGBT is formed and a semiconductor chip in which a diode is formed are mounted over a die pad. Then, the semiconductor chip and the semiconductor chip are connected by using a clip. The clip is arranged so as not to overlap with bonding pads formed at the semiconductor chip in a flat state. The bonding pads formed at the semiconductor chip are connected to electrodes by using wires.

Semiconductor device and method of manufacturing the same

A novel semiconductor device high in both heat dissipating property and connection reliability in mounting is to be provided. The semiconductor device comprises a semiconductor chip, a resin sealing member for sealing the semiconductor chip, a first conductive member connected to a first electrode formed on a first main surface of the semiconductor chip, and a second conductive member connected to a second electrode formed on a second main surface opposite to the first main surface of the semiconductor chip, the first conductive member being exposed from a first main surface of the resin sealing member, and the second conductive member being exposed from a second main surface opposite to the first main surface of the resin sealing member and also from side faces of the resin sealing member.

Semiconductor device having a sealing body and partially exposed conductors

A semiconductor device having a plurality of chips is reduced in size. In HSOP (semiconductor device) for driving a three-phase motor, a first semiconductor chip including a pMISFET and a second semiconductor chip including an nMISFET are mounted over each of a first tab, second tab, and third tab. The drains of the pMISFET and nMISFET over each tab are electrically connected with each other. Thus, two of six MISFETs can be placed over each of three tabs divided in correspondence with the number of phases of the motor, and they can be packaged in one in a compact manner. As a result, the size of the HSOP for driving a three-phase motor, having a plurality of chips can be reduced.

Semiconductor device

A semiconductor device manufacturing method in which a semiconductor chip is connected to first and second lead frames. Source and gate electrodes extending over a first main surface of the semiconductor chip are connected to first electrode plates of the first lead frame and a drain electrode on the second main surface of the semiconductor chip, opposite to the first main surface, is connected to a drain electrode plate of the second lead frame. A sealing body is formed to cover the semiconductor chip and lead frames, while leaving the top surface of the drain electrode plate exposed with respect to the sealing body. Unnecessary portions of the first and second lead frames are cut off and surface mounting terminals are formed from the portions of the first and second electrode plates projecting from the sealing body.

Manufacturing method of semiconductor device with surface mounting terminals

A semiconductor device has a sealing body formed of an insulating resin and a semiconductor chip positioned within the sealing body. A gate electrode and a source electrode are on a first main surface of the semiconductor chip and a back electrode (drain electrode) is on a second main surface thereof. An upper surface of a portion of a drain electrode plate that projects in a gull wing shape is exposed from the sealing body and a lower surface thereof is connected to the back electrode through an adhesive. A gate electrode plate projects in a gull wing shape on an opposite end side of the sealing body and is connected to the gate electrode within the sealing body. A source electrode plate projects in a gull wing shape on the opposite end side of the sealing body and is connected to the source electrode within the sealing body.

Semiconductor device with surface mounting terminals

Coupling reliability of a passive component is improved to increase the reliability of a semiconductor device. A first through hole is formed in a first electrode part of a first plate-like lead, and a second through hole is formed in a second electrode part of a second plate-like lead. As a result, at the first electrode part of the first plate-like lead, one external terminal of the passive component can be coupled to the first electrode parts on both sides of the first through hole while being laid across the first through hole. Also, at the second electrode part of the second plate-like lead, the other external terminal of the passive component can be coupled to the second electrode parts on both sides of the second through hole while being laid across the second through hole. Accordingly, at central portions both in the longitudinal and width directions of the passive component, the passive component is surrounded by sealing members. As a result, thermal stress applied to jointing materials such as solder can be reduced, improving the reliability of the semiconductor device (semiconductor package).

A semiconductor device has a semiconductor chip including first and second surfaces opposed to each other in a thickness direction of the semiconductor chip, wherein the first and second surfaces include first and second electrode surfaces respectively, and first and second electrically conductive members covering the first and second electrode surfaces respectively as seen in the thickness direction to be electrically connected to the first and second electrode surfaces respectively.

Semiconductor chip, electrically connections therefor

A semiconductor chip is sealed by resin without covering an outer terminal of a semiconductor device having a power transistor. A semiconductor chip having a power transistor is housed within a recess of a metal cap while a drain electrode on a first surface of the semiconductor chip is bonded to a bottom of the recess via a connection material. A gate electrode and a source electrode are formed on a second surface opposite to the first surface of the semiconductor chip, and the gate electrode and the source electrode are bonded with metal plate terminalsG,S via connection materials. In addition, the semiconductor chip is sealed by a resin sealing body with mounting-surfaces of the metal plate terminalsG,S being exposed. Mounting surfaces of the metal plate terminalsG,S and a third part of the metal cap are bonded to electrodes on a mounting boardvia connection materialsand

A semiconductor device in the form of a resin sealed semiconductor package is disclosed, wherein a gate terminal connected to a gate pad electrode formed on a surface of a semiconductor chip and a source terminal connected to a source pad electrode formed on the chip surface exposed to a back surface of a sealing resin portion, a first portion of a drain terminal connected to a back-surface drain electrode of the semiconductor chip is exposed to an upper surface of the sealing resin portion, and a second portion of the drain terminal formed integrally with the first portion of the drain terminal is exposed to the back surface of the sealing resin portion. When forming the sealing resin portion in such a semiconductor device, first the sealing resin portion is formed so as to also cover an upper surface of the first portion of the drain terminal and thereafter the upper surface side of the sealing resin portion is polished by liquid honing, thereby allowing the upper surface of the first portion of the drain terminal to be exposed on the upper surface of the sealing resin portion. Both heat dissipating property and production yield of the semiconductor device are improved.

Manufacturing method of semiconductor device

A semiconductor chip is sealed by resin without covering an outer terminal of a semiconductor device having a power transistor. A semiconductor chip having a power transistor is housed within a recess of a metal cap while a drain electrode on a first surface of the semiconductor chip is bonded to a bottom of the recess via a connection material. A gate electrode and a source electrode are formed on a second surface opposite to the first surface of the semiconductor chip, and the gate electrode and the source electrode are bonded with metal plate terminals. In addition, the semiconductor chip is sealed by a resin sealing body with mounting-surfaces of the metal plate terminals being exposed. Mounting surfaces of the metal plate terminals and a third part of the metal cap are bonded to electrodes on a mounting board.

A chip including a power MOS circuit in the high level side and a chip including a power MOS circuit in the low level side are accommodated within one sealing body. In this structure, the leads connecting the drain electrodes of the power MOS circuits in the high level and low level sides are set wide and are projected asymmetrically from both longer sides surfaces of the sealing body. Accordingly, the semiconductor device including a composite power MOSFET can be mounted easily.

Semiconductor package including a plurality of semiconductor chips therein

Growing community of inventors

Tamamura, Japan

Ichio Shimizu