Hitachi Automotive Systems, Ltd.

Hitachi, Ltd.

Ichiki Homma

Sujit S Phatak

Heming Chen

Yuan Xiao

Example implementations involve systems and methods which can involve storing interface (I/F) communication activity records of a plurality of simulation engines during execution of a co-simulation, and for a subsequent execution of the co-simulation, replacing one or more of the plurality of simulation engines with a simulation engine repeater configured to reproduce I/F communication activity from the stored I/F communication activity records corresponding to the replaced one or more of the plurality of simulation engines during the subsequent execution of the co-simulation and to log a real time consumed for execution of the reproduced I/F communication activity in the subsequent execution and a simulation time consumed for execution of the reproduced I/F communication activity for each simulation step, the real time determined based on a real time difference between a start of each simulation step and completion of synchronization with a co-simulator bus at an end of each simulation step.

Performance measurement methodology for co-simulation

Example implementations described herein are directed to systems and methods that include the storage of I/F communication activity during a co-execution and a repeater to reproduce such I/F communication activity. Thus in a subsequent re-execution of the simulation or applications, one or more of the simulations or applications utilized can be replaced with a repeater without requiring the full execution of the simulation or application, thereby saving license usage as well as requiring fewer hardware resources for execution.

Co-simulation repeater with former trace data

Example implementations described herein are directed to resolving issues related to the processor model in the S-PILS (Simulated Processor In the Loop Simulation) system, such as processor model correctness and simulation execution speed, by using the actual Central Processing Unit (CPU) board with silicon CPU instead of the virtual SoC model in the S-PILS.

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West Bloomfield, MI, United States of America

Ichiki Homma