Cypress Semiconductor Corporation

Ibrahim Yayla

Jason Faris Muriby

Joseph Andrew Cetin

Matthew D Sienko

Disclosed are a circuit and a method for an analog-to-digital conversion with programmable resolution. The circuit includes a resistor ladder comprising a plurality of resistors coupled to a plurality of comparators; wherein the resistor ladder is further coupled to a switch logic circuit and a plurality of current sources; and wherein the switch logic circuit is configured to control an operation of a plurality of switches to alter conversion resolution of the ADC, and an error correction circuit coupled to the outputs of the plurality of comparators, wherein the ADC is configured to perform a first conversion step and a second conversion step, and wherein the ADC is configured to perform only the first conversion step when programmed for lower conversion accuracy and higher conversion speed.

Analog-to-digital converter circuit and method with programmable resolution

A delay-locked loop ('DLL') having reduced susceptibility to false lock. The DLL includes a delay path coupled to delay an input signal. The delay path includes two or more variable delay cells coupled in series and a feedback node coupled to an output of one of the variable delay cells. An inverter is coupled to receive the input signal and to output an inverted signal. A feedback circuit is coupled to receive the inverted signal from the inverter and to receive a feedback signal from the feedback node. The feedback circuit monitors a phase difference between the inverted signal and the feedback signal to generate a delay control signal in response to the phase difference to adjust a variable delay of the delay path.

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Del Mar, CA, United States of America

Ibrahim Yayla