Nxp Usa, Inc.

Nxp B.v.

Nsp Usa, Inc.

Filtran LLC

Spx Filtran LLC

Ibrahim Khalil

Humayun Kabir

Bruce McRae Green

Damon G Holmes

Bernhard Grote

Kevin Kim

Hernan A Rueda

Charles John Lessard

Jeffrey Kevin Jones

David Cobb Burdeaux

Ramanujam Srinidhi Embar

Ning Zhu

Hussain Hasanali Ladhani

Vikas Shilimkar

Daniel Joseph Lamey

Partha Sarathi Chakraborty

Darrell Glenn Hill

Abdulrhman M S Ahmed

Yu-Ting David Wu

Philippe Renaud

Jeffrey Spencer Roberts

Freek Egbert Van Straten

Ricardo Uscola

Michele Lynn Miera

Henry Andre Christange

Ebrahim M Al Seragi

Conrad F Alfaro

Vasyl Kondratyuk

John G Eleftherakis

John W Shaw

Vikas Shilmkar

John Shaw

Placement of a field plate in a field-effect transistor is optimized by using multiple dielectric layers such that a first end of field plate is separated from a channel region of the transistor by a first set of one or more distinct dielectric material layers. A second end of the field plate overlies the channel region and a control electrode from which it is separated by the first set of dielectric layers and one or more additional dielectric layers. Relative positioning of the control electrode and the field plate are determined by a single processing step such that the field plate is self-aligned to the control electrode in order to reduce variations in transistor performance associated with manufacturing process variations.

Transistors with self-aligned source-connected field plates

An embodiment of a semiconductor device includes a semiconductor substrate, a first dielectric layer disposed over the upper surface of the semiconductor substrate, and a first current-carrying electrode and a second current-carrying electrode formed over the semiconductor substrate within openings formed in the first dielectric layer. A control electrode is formed over the semiconductor substrate and disposed between the first current-carrying electrode and a second current-carrying electrode and over the first dielectric layer. A first conductive element is formed over the first dielectric layer, adjacent the control electrode and between the control electrode and the second current-carrying electrode. A second dielectric layer is disposed over the control electrode and over the first conductive element. A second conductive element is disposed over the second dielectric layer and over the first conductive element. An opening in the second dielectric layer couples the first conductive element to the second conductive element.

Semiconductor device with conductive elements formed over dielectric layers and method of fabrication therefor

A transistor die includes input and output terminals and a source through-substrate via (TSV) between the input and output terminals. First and second primary drain contacts extend from the output terminal toward the input terminal past first and second sides, respectively, of the source TSV. An ancillary region is located adjacent to the source TSV, and boundaries of the ancillary region are defined by the source TSV, the first and second drain contacts, and one of the input terminal or the output terminal. The transistor further includes a primary transistor element, including a primary drain contact, a primary source contact, and a primary gate structure, located outside of the first ancillary region, and an ancillary transistor element, including an ancillary drain contact, an ancillary source contact, and an ancillary gate structure, located within the ancillary region.

Transistor die with primary and ancillary transistor elements

An embodiment of a semiconductor device includes a semiconductor substrate, a first dielectric layer, a first current-carrying electrode, and a second current-carrying electrode formed over the semiconductor substrate. A control electrode is formed over the semiconductor substrate and disposed between the first current-carrying electrode and the second current-carrying electrode. A conductive element formed over the first dielectric layer, adjacent the control electrode, and between the control electrode and the second current-carrying electrode, includes a first region formed a first distance from the upper surface of the semiconductor substrate and a second region formed a second distance from the upper surface of the semiconductor substrate. An insulating region is formed between the control electrode and the conductive element.

Semiconductor device with an insulating region formed between a control electrode and a conductive element and method of fabrication therefor

A device includes a semiconductor substrate, a source metallization over an active area of the semiconductor substrate, a through-substrate via electrically connected to the source metallization, and an input bond pad formed in the semiconductor substrate and spaced apart from the active area. The input bond pad is electrically connected to a set of gate structures. The device includes a first inductive coil over the semiconductor substrate between a first portion of the source metallization and a second portion of the source metallization and a first capacitor over the semiconductor substrate between the first portion of the source metallization and the second portion of the source metallization. The first inductive coil and the first capacitor are connected in series between the input bond pad and the through-substrate via.

Transistor with integrated passive components

A device having a reference transistor fabricated within the same semiconductor substrate as a primary transistor (e.g., configured for use in a radiofrequency amplifier or other active circuit) has a shared metallization area coupled to a current terminal of both transistors configured to shield a control terminal of the reference transistor from coupling of alternating current interference from alternating currents within the primary transistor.

Transistor circuits with shielded reference transistors

An embodiment of a semiconductor device includes a semiconductor substrate, a first dielectric layer disposed over the upper surface of the semiconductor substrate, and a first current-carrying electrode and a second current-carrying electrode formed over the semiconductor substrate within openings formed in the first dielectric layer. A control electrode is formed over the semiconductor substrate and disposed between the first current-carrying electrode and a second current-carrying electrode and over the first dielectric layer. A first conductive element is formed over the first dielectric layer, adjacent the control electrode and between the control electrode and the second current-carrying electrode. A second dielectric layer is disposed over the control electrode and over the first conductive element. A second conductive element is disposed over the second dielectric layer and over the first conductive element.

An amplifier module includes a module substrate with a mounting surface, a signal conducting layer, a ground layer, and a ground terminal pad at the mounting surface. A thermal dissipation structure extends through the module substrate. A ground contact of a power transistor die is coupled to a surface of the thermal dissipation structure. Encapsulant material covers the mounting surface of the module substrate and the power transistor die, and a surface of the encapsulant material defines a contact surface of the amplifier module. A ground terminal is embedded within the encapsulant material. The ground terminal has a proximal end coupled to the ground terminal pad, and a distal end exposed at the contact surface. The ground terminal is electrically coupled to the ground contact of the power transistor die through the ground terminal pad, the ground layer of the module substrate, and the thermal dissipation structure.

Amplifier modules and systems with ground terminals adjacent to power amplifier die

A transistor includes a source contact connected to a Through-Silicon Via (TSV). A drain contact is connected to a first pad. A gate structure is interposed between the source contact and the drain contact. A second pad is connected to the gate structure, the second pad comprising a first side diametrically opposed to a second side, and a third side interposed therebetween, the source contact proximal to the third side, a first portion of the first side and a second portion of the second side.

Transistor with center fed gate

A semiconductor device includes a die body having a frontside and a transistor having an active area formed in the die body, the active area being bounded by an outer periphery. An interconnect structure is formed over the frontside of the die body and contains patterned electrically conductive material defining first, second, and third contacts electrically coupled to first, second, and third subregions, respectively, within the active area of the transistor. A frontside input/output (I/O) interface is formed in an outer portion of the interconnect structure. The frontside I/O interface contains first, second, and third contact pads, the first contact pad being electrically connected to the first contact, the second contact pad being electrically connected to the second contact, and the third contact pad being electrically connected the third contact, wherein the third contact pad is positioned at a location overlying the active area of the transistor.

Transistor with flip-chip topology and power amplifier containing same

A power transistor die includes a semiconductor die with input and output die sides, and a transistor integrally formed in the semiconductor die between the input die side and the output die side, where the transistor has an input and an output (e.g., a gate and a drain, respectively). The power transistor die also includes an input bondpad and a first output bondpad integrally formed in the semiconductor die between the input die side and the transistor. The input bondpad is electrically connected to the input of the transistor. A conductive structure directly electrically connects the output of the transistor to the first output bondpad. A second output bondpad, which also may be directly electrically connected to the transistor output, may be integrally formed in the semiconductor die between the transistor and the output die side.

Transistor die with output bondpad at the input side of the die, and power amplifiers including such dies

A semiconductor device includes a semiconductor substrate, a first current-carrying electrode, a second current-carrying electrode, a first control electrode disposed between the first current-carrying electrode and the second current-carrying electrode, a third current-carrying electrode electrically coupled to the first current-carrying electrode, and a fourth current-carrying electrode adjacent the third current-carrying electrode. The third current-carrying electrode and the fourth current-carrying electrode are configured to support current flow from the third current-carrying electrode to the fourth current-carrying electrode parallel to a second direction. The fourth current-carrying element is electrically coupled to the second current-carrying electrode and a second control electrode. The second control electrode is electrically coupled to the first control electrode. A first crossing region is electrically coupled to the first control electrode and a second crossing region is electrically coupled to the fourth current-carrying electrode, wherein the second crossing region crosses a portion of the first crossing region.

Semiconductor device with a crossing region

A transistor includes a semiconductor substrate having first and second terminals. An interconnect structure, on an upper surface of the substrate, is formed of layers of dielectric material and electrically conductive material. The conductive material includes a first pillar connected with the first terminal, a second pillar connected with the second terminal, and a shield system between the first and second pillars. The shield system includes forked structures formed in at least two conductive layers of the interconnect structure and at least partially surrounding segments of the second pillar. The shield system may additionally include shield traces formed in a first conductive layer positioned between gate fingers and the first pillars and/or the shield system may include shield runners that are located in an electrically conductive layer that is below a topmost electrically conductive layer with the first pillar being connected to a runner in the topmost conductive layer.

Transistor with shield system including multilayer shield structure arrangement

A semiconductor device includes an active region formed in a substrate. The active region includes input fingers, output fingers, and common fingers disposed within the substrate and oriented substantially parallel to one another. An input port is electrically connected to the input fingers and an output port is electrically connected to the output fingers. A common region is electrically connected to the common fingers. At least one of the input and output ports is positioned within the active region between the input, output, and common fingers. The common region is interposed between a pair of the common fingers such that the common fingers of the pair are spaced apart by a gap, and at least one of the input and output ports is position in the gap.

Transistor with I/O ports in an active area of the transistor

Radio frequency (RF) power dies having flip-chip architectures are disclosed, as are power amplifier modules (PAMs) containing such RF power dies. Embodiment of the PAM include a module substrate and an RF power die, which is mounted to a surface of the module substrate in an inverted orientation. The RF power die includes, in turn, a die body having a frontside and an opposing backside, a transistor having active regions formed in the die body, and a frontside layer system formed over the die body frontside. The frontside layer system contains patterned metal layers defining first, second, and third branched electrode structures, which are electrically coupled to the active regions of the transistor. A frontside input/output interface is formed in an outer terminal portion of the frontside layer system and contains first, second, and third bond pads electrically coupled to the first, second, and third branched electrode structures, respectively.

Growing community of inventors

Gilbert, AZ, United States of America

Ibrahim Khalil