Advanced Micro Devices Corporation

Spansion Llc.

Fasl LLC

Ibrahim K Burki

Mohammed Anjum

Craig William Christian

Kelley Kyle Higgins

Alan L Stuber

A method of forming an integrated circuit includes providing a semiconductor substrate and forming a gate over the semiconductor substrate. A gate sidewall spacer is formed around the gate and a resist is deposited on the gate sidewall spacer with the gate sidewall spacer and the gate exposed. A portion of the gate within the gate sidewall spacer is removed and a gate silicide is formed within the curved gate sidewall spacer. A dielectric layer is formed over the gate silicide and a contact is formed to the gate silicide.

Method for containing a silicided gate within a sidewall spacer in integrated circuit technology

A semiconductor component having a substantially planar surface on which a film can be deposited and a method for manufacturing the semiconductor component. A layer of dielectric material is formed over a semiconductor substrate and a layer of polysilicon is formed on the layer of dielectric material. The polysilicon layer is patterned to form floating gate structures and expose portions of the layer of dielectric material. Additional dielectric material is formed over the floating gate structures and the exposed portions of the layer of dielectric material. The additional dielectric material is planarized such that it has a surface that is substantially contiguous with and coplanar with the floating gate structures. An oxide-nitride-oxide (ONO) dielectric structure or stack is formed on the surfaces of the floating gate structures and the dielectric material. A layer of polysilicon is formed on the ONO dielectric structure.

Floating gate semiconductor component and method of manufacture

An MOS device is provided using indium as a threshold adjust implant in the channel regions of an NMOS device and/or in the conductive gate overlying the channel region in a PMOS device. Indium ions are relatively immobile and achieve location stability in the areas in which they are implanted. They do not readily segregate and diffuse in the lateral directions as well as in directions perpendicular to the silicon substrate. Placement immobility is necessary in order to minimize problems of threshold skew and gate oxide thickness enhancement. Additionally, it is believed that indium atoms within the channel region minimize hot carrier effects and the problems associated therewith.

Active region implant methodology using indium to enhance short channel performance of a surface channel PMOS device

A field oxide is provided which purposefully takes advantage of fluorine mobility from an implanted impurity species. The field oxide can be enhanced or thickened according to the size (area and thickness) of the oxide. Fluorine from the impurity species provides for dislodgement of oxygen at silicon-oxygen bond sites, leading to oxygen recombination at the field oxide/substrate interface. Thickening of the oxide through recombination occurs after it is initially grown and implanted. Accordingly, initial thermal oxidation can be shortened to enhance throughput. The fluorine-enhanced thickening effect can therefore compensate for the shorter thermal oxidation time. Moreover, the thickened oxide regions are anistropically oxidized underneath existing thermally grown oxides and directly underneath openings between nitrides. The thickened oxides therefore do not cause additional shrinkage of the active areas which reside between field oxides.

Semicondutor having selectively enhanced field oxide areas and method

An improved method is provided for fabricating a metal silicide upon a semiconductor substrate. The method advantageously places a film of metal nitride upon the metal layer. The metal nitride layer and metal layer are sputter deposited within the same chamber without removing the substrate from the vacuum so as to prevent oxygen or moisture from contaminating the metal layer and causing oxides to form thereon. Furthermore, the metal nitride layer is reactively sputter deposited in a nitrogen/argon ambient to allow precise amounts of nitrogen to be deposited across uneven surface topography directly adjacent to the underlying metal layer. Excess nitrogen purposefully deposited within the metal nitride layer consumes a controlled depth of metal bond sites within the underlying metal layer so as to limit the amount of silicidation from underlying silicon or polysilicon into the metal thereby substantially eliminating or minimizing silicide shorting problems.

Integrated circuit fabrication using a metal silicide having a

An improved method is provided for fabricating a metal silicide upon a semiconductor substrate. The method utilizes ion beam mixing by implanting germanium to a specific elevation level within a metal layer overlying a silicon contact region. The implanted germanium atoms impact upon and move a plurality of metal atoms through the metal-silicon interface and into a region residing immediately below the silicon (or polysilicon) surface. The metal atoms can therefore bond with silicon atoms to cause a pre-mixing of metal with silicon near the interface in order to enhance silicidation. Germanium is advantageously chosen as the irradiating species to ensure proper placement of the germanium and ensuing movement of dislodged metal atoms necessary for minimizing oxides left in the contact windows and lattice damage within the underlying silicon (or polysilicon).

Method for forming a silicide using ion beam mixing

A method is provided for controlling growth of silicide to a defined thickness based upon the relative position of peak concentration density depth within a layer of titanium. The titanium layer is deposited over silicon and namely over the silicon junction regions. Thereafter the titanium is implanted with argon ions. The argon ions are implanted at a peak concentration density level corresponding to a depth relative to the upper surface of the titanium. The peak concentration density depth can vary depending upon the dosage and implant energies of the ion implanter. Preferably, the peak concentration density depth is at a midpoint between the upper and lower surfaces of the titanium or at an elevational level beneath the midpoint and above the lower surface of the titanium. Subsequent anneal of the argon-implanted titanium causes the argon atoms to occupy a diffusion area normally taken by silicon consumed and growing within overlying titanium. However, based upon the presence of argon, the diffusion length and therefore the silicide thickness is reduced to a controllable amount necessary for applications with ultra-shallow junction depths.

Method for low energy implantation of argon to control titanium silicide

A method is provided for reducing growth of silicide and the temperatures necessary to produce silicide. Germanium is implanted at a concentration peak density depth below the midline and above the lower surface of a metal layer receiving the implant. Subsequent anneal causes germanide to occupy an area above growing silicide such that consumption of silicon atoms is reduced, and that silicide is formed to a controlled thickness.

Germanium implant for use with ultra-shallow junctions

A PMOS device is provided having a diffusion barrier placed within a polysilicon gate material. The diffusion barrier is purposefully implanted to a deeper depth within the gate material than subsequently placed impurity dopants. The barrier comprises Ar atoms placed in fairly close proximity to one another within the gate conductor, and the impurity dopant comprises ions of BF.sub.2. F from the impurity dopant of BF.sub.2 is prevented from diffusing to underlying silicon-oxide bonds residing within the oxide bulk. By minimizing F migration to the bond sites, the present polysilicon barrier and method of manufacture can minimize oxygen dislodgment and recombination at the interface regions between the polysilicon and the gate oxide as well as between the gate oxide and silicon substrate.

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Austin, TX, United States of America

Ibrahim K Burki