Sun Microsystems, Inc.

Oracle International Corporation

Ian W Jones

Ivan E Sutherland

Charles E Molnar

William Stuart Coates

Robert J Drost

Charles E Molnar, Deceased

Josephus Ebergen

Mark R Greenstreet

Suwen Yang

Robert F Sproull

Jon Lexau

Jo C Ebergen

Hetal N Gaywala

The disclosed embodiments provide a system with a memory with an interface that includes tamper-evident features to enhance software security. The system includes a set of memory elements, wherein each memory element comprises storage for a set of bits that encode a data word and an associated validity indicator, which indicates whether the memory element contains a valid data word. It also includes a memory interface for the set of memory elements. This memory interface supports a conditional-write operation, which overwrites a data word in a memory element if an associated validity indicator indicates that the data word does not contain valid data, and which does not overwrite the data word and raises an error if the associated validity indicator indicates that the data word already contains valid data.

Memory interface with tamper-evident features to enhance software security

The disclosed embodiments provide a synchronizer latch circuit that facilitates resolving metastability issues. This synchronizer latch circuit includes a set of lightly loaded, cross-coupled transistors that form a metastable resolving and state-holding element that is coupled to two outputs. An incoming synchronization signal creates a voltage difference between the two outputs, but does not directly force a state change for the outputs. Instead, the data and clock inputs control transistors that allow neighboring power sources and/or ground network connections to weakly influence the outputs. The cross-coupled transistors then amplify the resulting voltage difference to generate valid output voltages, even when the data input and clock signal are received at roughly the same time. Thus, the synchronizer latch circuit facilitates rapidly resolving metastability and improving synchronizer performance.

Synchronizer latch circuit that facilitates resolving metastability

A serial-write, random-access read, memory addresses applications where the data in the memory may change more frequently than would make a PROM suitable, but that changes much less frequently than would require a RAM. This enables the circuit designer to optimize the memory for fast reads, and enables reads to be pipelined. One embodiment of the present invention provides a system that facilitates a serial-write, random-access read, memory. The system includes a plurality of memory cells and a serial access mechanism for writing data into the plurality of memory cells. The system also includes a parallel random-access mechanism for reading data from the plurality of memory cells.

Serial-write, random-access read, memory

One embodiment of the present invention provides a control queue for an asynchronous circuit that includes a number of control modules coupled together linearly to form the control queue. These control modules include a prior module, a present module, and a next module. The present module is configured to receive one or more forward-going inputs from the prior module and one or more reverse-going inputs from the next module. The present module asynchronously generates one or more forward-going outputs to the next module and one or more reverse-going outputs to the prior module. The modules within the control queue are constructed so that the latency of the forward-going signals through the control queue is equal to the latency of the reverse-going signals through the control queue.

Asynchronous control circuit with symmetric forward and reverse latencies

One embodiment of the present invention provides a system that facilitates phase-buffering on a bit-by-bit basis using a control queue. The system includes a control queue, wherein a stage in the control queue is configured to accept both a first control signal and a second control signal, wherein the first control signal and the second control signal are mutually exclusive, wherein the first control signal being asserted indicates the value of a corresponding bit is zero, while the second control signal being asserted indicates the value of the corresponding bit is one. A forward-transfer mechanism couples the first control signal or the second control signal from the input of the stage through storage elements to the output of the stage. A reverse transfer mechanism accepts an acknowledgement signal at the output of the stage and transfers the acknowledgement signal through a storage element to the input of the stage.

Apparatus and method for phase-buffering on a bit-by-bit basis using control queues

One embodiment of the present invention provides a system that limits a maximum repetition rate of an asynchronous circuit. The system operates by receiving a clock signal at a rate-controlling circuit for the asynchronous circuit from a source external to the asynchronous circuit. The system then uses the clock signal to limit the maximum repetition rate of the asynchronous circuit so that only a predetermined number of asynchronous transactions may take place during each cycle of the clock signal.

Method and apparatus for limiting the number of asynchronous events that occur during a clock cycle

One embodiment of the present invention provides a system that facilitates implementing a memory mechanism within an asynchronous switch fabric. The system includes a memory device, which does not preserve first-in, first-out semantics such as a random access memory or a stack. The system also includes a data destination horn, for routing data from a trunk line to a plurality of destinations. The memory device is one destination of the plurality of destinations. The system further includes a data source funnel, for routing data from a plurality of sources into the trunk line. The memory device is a source of the plurality of sources.

Apparatus and method for sequencing memory operations in an asynchronous switch fabric

A plurality of clock signal phases are distributed to a circuit and at least one jitter source is coupled between at least two selected clock phases of the plurality of clock signal phases to introduce a jitter between at least the selected two clock signal phases. In a specific embodiment, the clock distribution system provides N clock phases and, if the phases have an order, there is one jitter source provided between each of the first N&#x2212;1 phases and the following phase, so that each phase has a jitter relative to each other phase. Several implementations are possible for the jitter sources, which can be noise sources or pseudo-random noise sources, depending on which is easier to design and implement in a specific clock distribution system.

Jittery polyphase clock

Techniques for indicating partial fullness levels of a FIFO comprising a plurality of stages using a partial fullness detector, such as a m-out-of-n detector. According to an embodiment, the m-out-of-n detector is coupled to &ldquo;n&rdquo; stages of the FIFO and configured to output a partial fullness indicator signal based on the full/empty states of the stages coupled to the m-out-of-n detector. The m-out-of-n detector may be configured to output the partial fullness indicator signal in a first state when &ldquo;m&rdquo; stages coupled to the m-out-of-n detector are full, and to output the partial fullness indicator signal in a second state when &ldquo;m&rdquo; stages coupled to the m-out-of-n detector are empty. The number of full stages of the FIFO lies in a first range when the m-out-of-n detector outputs the signal in the first state, and in a second range when the m-out-of-n detector outputs the signal in the second state. The bounds for the ranges may be determined based on factors such as the input and output rate characteristics of the FIFO. The m-out-of-n detector may be used to indicate partial fullness levels for various FIFOs including linear flow-through FIFOs, serial-concurrent-serial (SCS) FIFOs, and the like.

Apparatus and method for generating a partial fullness indicator signal in a FIFO

One embodiment of the present invention provides a system that facilitates asynchronously routing data within a circuit. This system includes a data destination horn, for routing data from a trunk line to a plurality of destinations. This data destination horn includes a plurality of one-to-many switching elements organized into a tree of at least one level that fans out from the trunk line to the plurality of destinations. It also includes a plurality of memory elements for storing data in transit between the plurality of one-to-many switching elements. An asynchronous control structure is coupled to the data destination horn, and is configured to control the propagation of data through the data destination horn, so that when a given data item appears at an input of a memory element, the given data item is asynchronously latched into the memory element as soon space becomes available in the memory element without having to wait for a clock signal. One embodiment of the present invention additionally includes a data source funnel, for routing data from a plurality of sources into the trunk line. This data source funnel includes a plurality of many-to-one switching elements organized into a tree of at least one level that fans in from the plurality of sources to into the trunk line. It also includes a plurality of funnel memory elements for storing data in transit between the plurality of many-to-one switching elements. Moreover, the asynchronous control structure is additionally configured to control propagation of data through the data source funnel.

Switch fabric for asynchronously transferring data within a circuit

The Sharing arbiter is an arbiter which, under certain conditions, permits two or more Done signals to be received before the Sharing arbiter issues a grant signal and, under certain conditions, is permitted to issue more than one grant signal before receiving a Done signal. A Sharing arbiter can be implemented by adding a queue onto the Done input of a Sequencer arbiter. In a Sharing arbiter with a Sharing-number of N and K request inputs, the Sharing arbiter is permitted to issue M grant signals concurrently if M input requests have been received (where M&lE;K and M&lE;N) without enforcing mutual exclusion between the grants if at least M Done signals have also been received. Where less than M Done signals have been received (P Done signals, for example), the Sharing arbiter arbitrates among the M input requests and is permitted to issue P grant signals concurrently.

Sharing arbiter

One embodiment of the present invention provides a system that facilitates prototyping asynchronous circuits. The system first receives a design of an asynchronous circuit, which includes asynchronous cells. The system maps the asynchronous cells of the asynchronous circuit onto clocked synchronous cells within a logic array or programmable logic array device such as standard-cell gate-arrays and field-programmable gate-arrays. The mapping delays the generation of the asynchronous clock events until the next clock event, thus preserving the full functionality of the asynchronous circuit. The system then implements the mapped circuit on the synchronous device to perform the functions that are mapped from the asynchronous circuit. Finally, the system operates the synchronous device, and the results of operating the synchronous device are used to verify the design of the asynchronous circuit.

Method for prototyping asynchronous circuits using synchronous devices

A layered counterflow pipeline structure is described in which sub-tasks performed at each stage in a counterflow pipeline processor are separated into different layers. As words flow through the counterflow pipeline processor, they are divided into partial words which are supplied to the different layers, GET, CHECK and PROCESS, for appropriate handling by that portion of each stage. In the GET layer, partial words passing through each stage are analyzed to determine whether they constitute an encounter pair. In the CHECK layer a determination is made as to whether the word selected by the GET layer requires further modification. Finally, in the PROCESS layer operations are performed on the words themselves based upon control messages from the other layers. The layers of the processor communicate with each other using suitable communication paths such as First In First Out registers.

Layered counterflow pipeline processor with anticipatory control

An arbiter is disclosed for determining a sequence of signals indicative of events occurring variously on at least two input connections. The arbiter includes a first input connection and a second input connection for carrying the signals indicative of events. A first input queue for storing representations of events that are waiting to be processed is connected to the first input connection, and a second input queue also for storing representations of events that are waiting to be processed is connected to the second input connection. An arbitration circuit coupled to the first input queue and to the second input queue receives the representations of events from each of the queues and determines the temporal order of occurrence of the event representations in the queues when the events arrive at time intervals greater than a specified amount, and arbitrarily assigns a sequence to one or the other of the events from the queues when the events arrive at time intervals equal to or less than the specified amount. In response the arbitration circuit reports the temporal order or arbitrary sequence as a sequence of output signals and removes each event representation from the appropriate queue when reporting its temporal order or sequence.

Observing arbiter

Several designs of a stage for use in a FIFO pipeline are disclosed. Each stage includes a latch that is capable of latching a data element and capable of transitioning between a transparent state and an opaque state. The stages also include a control circuit capable of announcing the availability of the data element to the next stage as soon as the data element has propagated through the latch and without any latching or unlatching action of the latch prior to the announcement of the availability of the data element. In other words, if the latch of a stage is transparent and receives a signal Ri from the previous stage, the control circuit of the stage generates signal Ro after receiving signal Ri, thus enabling the next stage to latch the data element before the current stage has itself latched that data element. This feature is possible because the next stage receives at the input Din of latch block the same data element that appears at the input Din of the current latch block when the current latch block is transparent.

Growing community of inventors

Palo Alto, CA, United States of America

Ian W Jones