Applied Materials, Inc.

Intevac, Inc.

Seiko Epson Corporation

Lam Research Corporation

Shah, Vinay

Bluck, Terry

Riposan, Alex

Latchford, Ian

Ian Scot Latchford

Christopher Dennis Bencher

Yuxiang May Wang

Timothy Weidman

Christopher S Ngai

Michael Robert Rice

Kevin P Fairbairn

Terry Bluck

Vinay K Shah

Isamu Namose

Mario Dave Silvetti

Chester A Szwejkowski

Kazumi Tsuchida

James S Papanu

Thomas E Nowak

Tsutomu Tanaka

Jian J Chen

Michael D Armacost

Martin Jay Seamons

Ping Xu

Steve S Mak

Charles S Rhoades

Peter Chang-Lin Hsieh

Jason K Foster

Mary Anne Plano

Brian Shieh

Alexandru Riposan

Bok Heon Kim

Alex Riposan

Zahra H Amini

Wesley George Lau

James Dillard

Victoria Yu-Wang

Heath B DeShong

Karen A Williams

Carmel Ish-Shalom

Patrica Vasquez

David J Hemker

Brigitte Petit

A method for removing and preventing defects on surfaces of a component of a substrate processing chamber includes loading the component into a vacuum chamber and, with the component loaded within the vacuum chamber, baking the component at a baking temperature during a first predetermined period to remove water and defects from the surfaces of the component, and purging the component within the vacuum chamber during at least one second predetermined period to remove the defects from the vacuum chamber.

Ultra-low defect part process

A system for processing substrates in plasma chambers, such that all substrates transport and loading/unloading operations are performed in atmospheric environment, but processing is performed in vacuum environment. The substrates are transported throughout the system on carriers. The system's chambers are arranged linearly, such that carriers move from one chamber directly to the next. A conveyor, placed above or below the system's chambers, returns the carriers to the system's entry area after processing is completed. The carriers are configured for supporting substrates of different sizes. The carriers are also configured for flipping the substrates such that both surfaces of the substrates may be processed.

System and method for bi-facial processing of substrates

An arrangement for supporting substrates during processing, having a wafer carrier with a susceptor for supporting the substrate and confining the substrate to predetermined position. An inner mask is configured for placing on top of the substrate, the inner mask having an opening pattern to mask unprocessed parts of the substrate, but expose remaining parts of the substrate for processing. An outer mask is configured for placing on top of the inner mask, the outer mask having an opening that exposes the part of the inner mask having the opening pattern, but cover the periphery of the inner mask.

Dual-mask arrangement for solar cell fabrication

A method of forming an integrated circuit using an amorphous carbon film. The amorphous carbon film is formed by thermally decomposing a gas mixture comprising a hydrocarbon compound and an inert gas. The amorphous carbon film is compatible with integrated circuit fabrication processes. In one integrated circuit fabrication process, the amorphous carbon film is used as a hardmask. In another integrated circuit fabrication process, the amorphous carbon film is an anti-reflective coating (ARC) for deep ultraviolet (DUV) lithography. In yet another integrated circuit fabrication process, a multi-layer amorphous carbon anti-reflective coating is used for DUV lithography.

Method of depositing an amorphous carbon layer

A method for forming a patterned amorphous carbon layer in a semiconductor stack, including forming an amorphous carbon layer on a substrate and forming a silicon containing photoresist layer on top of the amorphous carbon layer. Thereafter, the method includes developing a pattern transferred into the resist layer with a photolithographic process and etching through the amorphous carbon layer in at least one region defined by the pattern in the resist layer, wherein a resist layer hard mask is formed in an outer portion of the photoresist layer during etching.

Photolithography scheme using a silicon containing resist

Methods for forming a patterned layer of amorphous carbon on a substrate are described. A layer of amorphous carbon may be formed on the substrate. A layer of electron sensitive resist may be formed on top of the amorphous carbon layer. A pattern transferred into the electron sensitive resist layer with an electron beam writing process is developed. During the electron beam writing process, electrons may be conducted away from the writing area through the amorphous carbon layer. The amorphous carbon layer may be etched through in at least one region defined by the pattern developed into the layer of electron sensitive resist material. For some embodiments, the amorphous carbon layer may be formed by chemical vapor deposition. For some embodiments, the layer of electron sensitive resist may be hydrogen silsesquioxane (HSQ).

Conductive bi-layer e-beam resist with amorphous carbon

Methods and apparatus for cleaning semiconductor processing equipment. The apparatus include both local and remote gas dissociators coupled to a semiconductor processing chamber to be cleaned. The methods include introducing a precursor gas into the remote dissociator where the gas is dissociated and introducing a portion of the dissociated gas into the chamber. Another portion of the dissociated gas which re-associates before introduction into the chamber is also introduced into the chamber where it is again dissociated. The dissociated gas combines with contaminants in the chamber and is exhausted from the chamber along with the contaminants.

Enhanced remote plasma cleaning

Embodiments of the invention generally provide a method of forming an air gap between conductive elements of a semiconductor device, wherein the air gap has a dielectric constant of approximately 1. The air gap may generally be formed by depositing a dielectric material between the respective conductive elements, depositing a porous layer over the conductive elements and the dielectric material, and then stripping the dielectric material out of the space between the respective conductive elements through the porous layer, which leaves an air gap between the respective conductive elements. The dielectric material may be, for example, an amorphous carbon layer, the porous layer may be, for example, a porous oxide layer, and the stripping process may utilize a downstream hydrogen-based strip process, for example.

Airgap for semiconductor devices

Method for depositing an amorphous carbon layer

A process for passivating, and optionally stripping and inhibiting corrosion of an etched substrate (20), is described. In the process, a substrate (20) having etchant byproducts (24) thereon, is placed into a vacuum chamber (52), and passivated in a multicycle passivation process comprising at least two passivating steps. In each passivating step, passivating gas is introduced into the vacuum chamber (52) and a plasma is generated from the passivating gas. When the substrate also has remnant resist (26) thereon, the resist (26) is stripped in a multicycle passivation and stripping process, each cycle including a passivating step and a stripping step. The stripping step is performed by introducing a stripping gas into the vacuum chamber (52) and generating a plasma from the stripping gas. In the multicycle process, the passivating and optional stripping steps, are repeated at least once in the same order that the steps were done. Alternatively, the substrate (20) can also be passivated in a single cycle process using a passivating gas comprising water vapor, oxygen, and nitrogen. Optionally, corrosion of the substrate is further inhibited by introducing an amine vapor into the vacuum chamber (52) so that amine adsorps onto the substrate (20), forming a corrosion inhibition amine layer on the surface of the substrate (20).

Passivating, stripping and corrosion inhibition of semiconductor

The invention comprises an improvement in the process wherein a polysilicon layer, which is formed over a step on an integrated circuit structure and masked with a photoresist, is anisotropically etched to remove the exposed portions of the polysilicon layer leaving sidewall residues of a polymerized silicon/oxide-containing material adjacent the polysilicon lines. The improvement comprises treating the integrated circuit substrate with an aqueous ammonium-containing base/peroxide solution to remove the residues of polymerized silicon/oxide-containing material, without undercutting the remaining polysilicon.

Process for removal of residues remaining after etching polysilicon

A process is described for removing, from an integrated circuit structure, photoresist remaining after one or more metal etch steps which also removes or inactivates a sufficient amount of remaining chlorine-containing residues from the previous metal etch steps to inhibit corrosion of remaining metal for at least 24 hours. The process includes a first stripping step which comprises flowing NH.sub.3 gas through a microwave plasma generator into a stripping chamber which contains the integrated circuit structure while maintaining a plasma in the plasma generator. O.sub.2 gas (and optionally NH.sub.3 gas) is flowed through the plasma generator into the stripping chamber during a second step while maintaining the plasma in the plasma generator.

Method for removal of photoresist over metal which also removes or

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Sunnyvale, CA, United States of America

Ian Scot Latchford