Tilera Corporation

Arm Limited

Mellanox Technologies, Ltd.

Ezchip Technologies Ltd.

Apical Limited

Tilera Corperation

Ian Rudolf Bratt

Matthew Mattina

Anant Agarwal

Carl Ramey

Christopher D Metcalf

Liewei Bao

Chyi-Chang Miao

Alexander Eugene Chalfin

Andreas Due Engh-Halstvedt

Håkan Lars-Göran Persson

Ole Henrik Jahren

Eric Kunze

Lingchuan Meng

Leiwei Bao

Mark B Rosenbluth

Jorn Nystad

John Wakefield Brothers

Andrew Brookfield Swaine

Bruce James Mathewson

Andrew Christopher Rose

David M Wentzlaff

Paul Nicholas Whatmough

Olof Henrik Uhrenholt

Edvard Fielding

Christopher J Jackson

Bruce Edwards

Antony John Harris

Richard Schooler

Andreas Hansson

Paul Stanley Hughes

William Robert Stoye

Mladen Wilder

Patrick Robert Griffin

Damian Piotr Modrzyk

Daniel Adam Sara

Jared Smolens

Kenneth M Steele

Metin Gokhan Ünal

Shane Bell

Danny Loh

Thomas Jeremy Olson

Antonio Garcia Guirado

John A Amann

Alex Kornienko

Jens Olson

Mathew Hostetter

Andreas Loeve Selvik

Richard Conlin

Sigurd Røed Scheistrøen

Ben Harrison

Kevin Joyce

Christine Deignan

Tianmu Li

Jonathan Adam Lawton

A processor arranged to compress neural network activation data comprising an input module for obtaining neural network activation data. The processor also comprises a block creation module arranged to split the neural network activation data into a plurality of blocks; and a metadata generation module for generating metadata associated with at least one of the plurality of blocks. Based on the metadata generated a selection module selects a compression scheme for each of the plurality of blocks, and a compression module for applying the selected compression scheme to the corresponding block to produce compressed neural network activation data. An output module is also provided for outputting the compressed neural network activation data.

Compression of neural network activation data

The present disclosure advantageously provides a system and a method for convolving data in a quantized convolutional neural network (CNN). The method includes selecting a set of complex interpolation points, generating a set of complex transform matrices based, at least in part, on the set of complex interpolation points, receiving an input volume from a preceding layer of the quantized CNN, performing a complex Winograd convolution on the input volume and at least one filter, using the set of complex transform matrices, to generate an output volume, and sending the output volume to a subsequent layer of the quantized CNN.

Efficient convolutional neural networks

An apparatus and method are disclosed for managing cache coherency. The apparatus has a plurality of agents with cache storage for caching data, and coherency control circuitry for acting as a point of coherency for the data by implementing a cache coherency protocol. In accordance with the cache coherency protocol the coherency control circuitry responds to certain coherency events by issuing coherency messages to one or more of the agents. A given agent is arranged, prior to entering a given state in which its cache storage is unused, to perform a flush operation in respect of its cache storage that may cause one or more evict messages to be issued to the coherency control circuitry. Further, once all evict messages resulting from performance of the flush operation has been issued, the given agent issues an evict barrier message to the coherency control circuitry. The apparatus ensures that the evict barrier message is only processed by the coherency control circuitry once all evict messages resulting from performance of the flush operation have been processed by the coherency control circuitry. When processing the evict barrier message, the coherency control circuitry issues a barrier response message to the given agent once it is determined that there are no outstanding coherency messages, and the given agent defers entering the given state until at least the barrier response message is received.

Technique for managing coherency when an agent is to enter a state in which its cache storage is unused

A circuit and method are provided for performing convolutional neural network computations for a neural network. The circuit includes a transposing buffer configured to receive actuation feature vectors along a first dimension and to output feature component vectors along a second dimension, a weight buffer configured to store kernel weight vectors along a first dimension and further configured to output kernel component vectors along a second dimension, and a systolic array configured to receive the kernel weight vectors along a first dimension and to receive the feature component vectors along a second dimension. The systolic array includes an array of multiply and accumulate (MAC) processing cells. Each processing cell is associated with an output value. The actuation feature vectors may be shifted into the transposing buffer along the first dimension and output feature component vectors may shifted out of the transposing buffer along the second dimension, providing efficient dataflow.

Systolic convolutional neural network

When processing graphics primitives in a graphics processing system, the render output is divided into a plurality of regions () for rendering, each region () comprising a respective area of the render output; and for sets of one or more primitives to be rendered, it is determined for which of the plurality of regions of the render output () the primitive(s) should be rendered; and for each region of the render output () it is determined the primitive(s) should be rendered for, geometry data for the primitive(s) is stored in memory in a respective data structure () along with an indication of state data that is to be used for rendering the primitive(s) for the region, such that the geometry data for the primitive(s) to be rendered is stored in a respective, different data structure () for each different region of the render output () it is determined the primitive(s) should be rendered for.

Graphics processing systems

A display controllerin a data processing system includes a timewarp module (transformation circuitry)that is operable to perform timewarp processing of a rendered framegenerated by a graphics processor (GPU)for provision to a display panel. The timewarp module (transformation circuitry)operates to transform an input surfaceread by the display controllerbased on received view orientation data to provide an appropriately 'timewarped' transformed version of the input surface as an output transformed surface for display on the display

Data processing systems

An apparatus and method are provided for issuing access requests to a memory controller for a memory device whose memory structure consists of a plurality of sub-structures. The apparatus has a request interface for issuing access requests to the memory controller, each access request identifying a memory address. Within the apparatus static abstraction data is stored providing an indication of one or more of the sub-structures of the memory device, and the apparatus also stores an indication of outstanding access requests issued from the request interface. Next access request selection circuitry is then arranged to select from a plurality of candidate access requests a next access request to issue from the request interface. That selection is dependent on sub-structure indication data that is derived from application of an abstraction data function, using the static abstraction data, to the memory addresses of the candidate access requests and the outstanding access requests. Such an approach enables the apparatus to provide a series of access requests to the memory controller with the aim of enabling the memory controller to perform a more optimal access sequence with regard to the memory device.

Apparatus and method for issuing access requests to a memory controller

A filter comprises interface circuitry, to intercept coherency protocol transactions exchanged between a master device comprising a first cache and an interconnect for managing coherency between the first cache and at least one other cache or other master device. The filter has filtering circuitry for filtering the coherency protocol transactions in dependence on memory access permission data defining which regions of an address space the master device is allowed to access.

Filtering coherency protocol transactions

A plurality of processor tiles are provided, each processor tile including a processor core. An interconnection network interconnects the processor cores and enables transfer of data among the processor cores. An extension network connects input/output ports of the interconnection network to input/output ports of one or more peripheral devices, each input/output port of the interconnection network being associated with one of the processor tiles such that each input/output port of the interconnection network sends input data to the corresponding processor tile and receives output data from the corresponding processor tile. The extension network is configurable such that a mapping between input/output ports of the interconnection network and input/output ports of the one or more peripheral devices is configurable.

Configuring routing in mesh networks

Managing data in a computing system comprising one or more cores includes: providing a cache in each of one or more of the cores that includes multiple storage locations; storing data of a first type of multiple types of data in a selected storage location of a first cache of a first core that is selected according to status information associated with the first cache, and updating the status information; and storing data of a second type of the multiple types of data in a storage location within a subset of fewer than all of the storage locations of the first cache and managing the status information to ensure that subsequent data of the second type received by the first core for storage in the first cache is stored in the storage location within the subset.

Managing cache access and streaming data

A method of operating a data processing system comprises maintaining record of a set of processing passes to be performed by processing pass circuitry of the data processing system. The method comprises performing cycles of operation in which it is considered whether or not the data required for a subset of processing passes is stored in a local cache. The subset of processing passes that is considered in a subsequent scan of the record comprises at least one processing pass that was not considered in the previous scan of the record, regardless of whether or not the data considered in the previous scan is determined as being stored in the cache. The method provides an efficient way to identify processing passes that are ready to be performed.

Data processing systems using both a cache and a buffer for processing data

Interconnect circuitry and a method of operating the interconnect circuitry are provided, where the interconnect circuitry is suitable to couple at least two master devices to a memory, each comprising a local cache. Any access to the memory mediated by the interconnect circuitry is policed by a memory protection controller situated between the interconnect circuitry and the memory. The interconnect circuitry modifies a coherency type associated with a memory transaction received from one of the master devices to a type which ensures that when a modified version of a copy of a transaction target specified by the issuing master device is stored in a local cache of another master device an access to the transaction target in the memory must take place and therefore must be policed by the memory protection controller.

Enforcing data protection in an interconnect

A multicore processor comprises a plurality of cache memories, and a plurality of processor cores, each associated with one of the cache memories. Each of at least some of the cache memories is configured to maintain at least a portion of the cache memory in which each cache line is dynamically managed as either local to the associated processor core or shared among multiple processor cores.

Caching in multicore and multiprocessor architectures

Communicating among cores in a computing system comprising a plurality of cores, each core comprising a processor and a switch, includes: routing a packet from a core or from a device coupled to at least one core to a destination over a route including one or more cores, with an order of dimensions associated with the route being selected dynamically upon construction of the packet; routing the packet to a first core in the route over the first selected dimension; and routing the packet from the first core to the destination over the second dimension.

Low latency dynamic route selection

Growing community of inventors

Castle Rock, CO, United States of America

Ian Rudolf Bratt