Vlsi Technology, Inc.

University of Utah Research Foundation

Vsli Technology, Inc.

Fort Supply Ip, LLC

Philips Electronics North America Corporation

Bourns Incorporated

Fort Supply Technologies, LLC

Ian Robert Harvey

Calvin T Gabriel

Xi-Wei Lin

Malcolm Randall Harvey

Nephi Taylor Harvey

Brian Baker

Satyendra S Sethi

Henry C Lee

Linda Leard

Subhas Bothra

Milind Ganesh Weling

Harlan Lee Sur, Jr

Tammy D Zheng

Charles Franklin Drill

Ramiro Solis

David E Henderson

Ronald Wayne Boutte

Michael Frederick Ehman

Charles Fisher

Taylor M Meacham

James Craig Stephenson

Alonso P Moreno

Iain E Harvey

Gary S Goldberg

Christopher F Smith

Abhijit Mondal

In a method and system for managing a social group, the method includes determining a group member behavior from a member position relative to the social group, and inferring a member state from the member behavior. Spatial, spatio-temporal, and biometric data may be used. A social group management system includes an inference engine that infers a member state from the behavior of a monitored member. Another social group management method includes characterizing a first monitored member of the social group as a first discrete element; characterizing at least a second monitored member of the social group as at least a second discrete element; and determining a characteristic displacement between the first monitored member and at least the second monitored member in accordance with a discrete element method.

Social group management system and method therefor

Electrophysiological recording systems for analysis of cultured cells include an recording device and a housing for supporting the electrophysiological recording device. The device has a porous membrane with top and bottom surfaces and a plurality of pores extending between the top and bottom surfaces. The porous membrane defines a first cell culture region disposed on the top surface and an opposed second cell culture region disposed on the bottom surface. The electrophysiological recording device has a plurality of electrodes positioned on the porous membrane in between a first insulation layer and a second insulation layer. The plurality of electrodes extend to the first cell culture region of the porous membrane. Recording ends of the electrodes measure electrical properties of cells cultured within the first and second cell culture regions, while the contact ends of the electrodes are positioned in electrical communication with data acquisition equipment.

Electrophysiological recording system and methods of using same

A flexible lens may be actuated to change its focal length by a deployable lens actuator. The lens actuator translates a rotational motion of an outer frame into a linear radial motion of a plurality of linear elements. The linear elements have fixed pins, which may be slidably coupled to cam pockets in the outer frame. The cam pockets have a gradually varying distance from the center of the outer frame. The rotation of the outer frame thus drives the cam pockets to slide about the pins, thereby causing radial motions of the linear elements. The linear elements stretch a flexible lens, thereby changing a curvature of the flexible lens.

Lens actuator

A microelectromechanical system (MEMS) device includes an actuator having a plurality of charge collection elements. At least one of the charge collection elements is configured to build up electrical charges by directly interacting with an energy field thereby actuating the MEMS through Coulombic interactions. An actuator for a MEMS device is configured to actuate the MEMS device through Coulombic interactions by pumping charges to the actuator when subject to an energy field. A method of actuating a MEMS device includes irradiating an actuator of the MEMS device with an energy field thereby building up electrical charges on the actuator, and actuating the MEMS device with Coulomb forces from the built up electrical charges.

MEMS devices and systems actuated by an energy field

RFID animal ear tag

A method for forming a semiconductor structure on an active area mesa with minimal loss of field oxide deposited in isolation trenches adjacent the mesa. The trench insulating material is protected by an etch barrier layer having at least a partial resistance to etchants used in further device processing steps. The barrier layer may also be deposited over the surface of the substrate to protect it from damage during device processing. The barrier layer may be removed by an etchant having a selectivity for the barrier layer over that of the surrounding device elements. Final processing of the device may be completed once the barrier layer is removed.

Method for fabrication of a semiconductor device

An inductive component includes a substrate on the surface of which is a lower insulation layer having a shallow concavity or trench, a first plurality of conductive elements formed in the trench, a magnetic core formed over the first plurality of conductive elements, and a second plurality of conductive elements formed over the core. The first and second pluralities of conductive elements are connected to each other so as to form an inductive coil around the core. First and second core insulation layers are disposed between the core and the first and second pluralities of conductive elements, respectively. The component is fabricated by a method in which it is built up in the trench using thin film techniques. A first array of conductors is patterned over the lower insulation layer, and a first core insulation layer is applied over the first conductor array. A magnetic core is formed on top of the first core insulation layer, and a second core insulation layer is applied over the core. A second array of conductors is patterned on top of the second core insulation layer so that the ends of the conductors in the first and second arrays contact each other to form an inductive coil around the core. The formation of either the first or second plurality of conductors may coincide with the formation of the metal conductor layer in the manufacture of a semiconductor integrated circuit, whereby the inductive component can be manufactured as part of the integrated circuit.

Integrated inductive components and method of fabricating such components

A system for dislodging by-product agglomerations from a polishing pad of a chemical mechanical polishing (CMP) machine. The present invention is used in conjunction with a CMP machine that polishes semiconductor wafers. Specifically, an embodiment of the dislodging system in accordance with the present invention includes a megasonic nozzle which is adapted to effectively dislodge polishing by-product agglomerations and particles from the grooves and micro-pits of the surface of a polishing pad through the application of an output stream of extremely agitated fluid (e.g., deionized water). One embodiment of the megasonic nozzle in accordance with the present invention includes two piezoelectric transducers which operate at a resonant frequency to produce the extremely agitated stream of fluid. A fluid line is connected to the megasonic nozzle and a fluid source in order to convey fluid to the megasonic nozzle. Within one embodiment of the present invention, a megasonic nozzle is mounted on a conditioner arm of a CMP machine near the end effector. As the polishing pad of the CMP machine rotates, the megasonic nozzle and the end effector translationally move towards and away from the center of the polishing pad such that the output stream of the megasonic nozzle covers nearly the entire surface of the polishing pad.

System for dislodging by-product agglomerations from a polishing pad of a chemical mechanical polishing machine

Disclosed is a method for inspecting electrical interconnections in a multi-level semiconductor device. The method includes forming an interconnect structure in the multi-level semiconductor device. The interconnect structure has a lower metallization layer that lies in a lower level and an upper metallization layer that lies in an upper level. The method includes performing a passive voltage contrast operation using a scanning electron microscope to produce an image of the upper metallization layer of the interconnect structure. The method further includes inspecting the image produced by the scanning electron microscope to determine whether a misalignment is present in the interconnect structure. Additionally, the scanning electron microscope applies a beam of electrons over a selected portion of the interconnect structure, and secondary electrons are emitted off of the upper metallization layer in response to the beam of electrons. Therefore, by examining the intensity levels of the secondary electrons, it is possible to determine whether misalignments have occurred.

Method and apparatus for detecting misalignments in interconnect structures

A test device and method for determining parameters of a plurality of vias formed into a dielectric material making contact to a buried conductive layer. The present invention is comprised of a sample structure disposed within the material through which a plurality of vias are to be formed. The sample structure is adapted to enhance secondary electron yield from the via bottom during a scanning electron microscope examination of the vias. Additionally, the plurality of vias to be formed are disposed intentionally offset with respect to the sample structure. As a result, the enhanced secondary electron yield from the sample structure characterizes the degree of misalignment present in the via formation process. In so doing, the present invention simultaneously quantifies the critical dimension of the vias, the alignment/registration of the via formation process, and determines whether or not the vias are etched to a minimum desired depth.

Via alignment, etch completion, and critical dimension measurement method and structure

A process for making an integrated circuit is disclosed. This technique includes electrically interconnecting a pair of adjacent transistors positioned along a semiconductor substrate by coating with an oxide layer, planarizing the layer, then forming a trench exposing a contact region for each transistor. This trench is filled with a metal, such as tungsten to provide an electrical interconnection of the contact regions. The metal is then planarized to be approximately coplanar with the planarized oxide layer. Metal gate electrodes are formed at the same time as the interconnection. Additional processing includes depositing an IMO layer over the planarized metal and oxide and defining additional interconnections through the IMO layer.

Metallization technique for gate electrodes and local interconnects

An integrated circuit includes a substrate with doped regions, a patterned polysilicon layer defining contacts and local interconnects, a submetal dielectric, a two-metal layer metal interconnect structure with an intermetal dielectric layer, and a passivation layer. Like the dielectric layers, the passivation layer is optically transparent, thick, and planarized. Because of this, laser energy can be directed through the passivation layer to fuse two conductors of the top metal layer without delaminating the passivation layer. In addition, laser energy is directed through the passivation layer and the intermetal dielectric to fuse pairs of conductors in the lower metal layer. Thus, the present invention provides for reliable convenient circuit modification without disturbing dielectric and exposing metal features to moisture and other contaminants.

Custom laser conductor linkage for integrated circuits

The present invention relates to multilevel integrated circuit interconnection techniques. An integrated circuit having a number of electronic components along a semiconductor substrate and a first connection layer having a first number of conductors in selective electrical contact with the components is provided. A first insulative layer is formed on the first connection layer with a first pattern of openings therethrough. A second connection layer is established that has a second number of conductors selectively interconnected to the first conductors through the first pattern of openings. A second insulative layer is formed on the first connection layer with a second pattern of openings therethrough. A third connection layer is formed on the second insulative layer having a third dielectric and a third number of conductors selectively interconnecting the second conductors. The first and second insulative layers are preferably etch selective to a dielectric included in the first, second, and third connection layers; and crossover, crossunder, or local interconnects are formed in a different connection layer than routing interconnects to facilitate higher interconnection density.

Growing community of inventors

Kaysville, UT, United States of America

Ian Robert Harvey