International Business Machines Corporation

Globalfoundries Inc.

Other

Infineon Technologies North America Corp.

Ian P Stobert

James A Culp

Shayak Banerjee

Dureseti Chidambarrao

Lars W Liebmann

Alan Edward Rosenbluth

Rasit Onur Topaloglu

Jeanne P Bickford

Stephen Edward Greco

Paul Christian Parries

Ioana C Graur

Klaus Herold

Ayman Hamouda

Dmitry A Vengertsev

Azalia A Krasnoperova

Mohamed Elsayed Mohamed Lotfy Gheith

Steven M Fox

Donald J Hathaway

The present disclosure generally relates to semiconductor structures and, more particularly, to curvilinear mask models and methods of manufacture. The method includes: calibrating, by a computing device, machine learning models for silicon photonics applications; retargeting, by the computing device, designs in a layout for the silicon photonics applications by applying the machine learning models to the designs; and repairing, by the computing device, unmatching shapes in the retargeted designs to generate final curvilinear mask shapes for the silicon photonics application.

Curvilinear mask models

Candidate layout patterns can be generated using a generative model trained based on known data, such as historical hot spot data, features extraction, and geometrical primitives. The generative model can be sampled to obtain candidate layouts that can be ranked and repaired using error optimization, design rule checking, optical proximity checking, and other methods to ensure that resulting candidates are manufacturable.

Generative learning for realistic and ground rule clean hot spot synthesis

Apparatus, method and computer program product for reducing overlay errors during a semiconductor photolithographic mask design process flow. The method obtains data representing density characteristics of a photo mask layout design; predicts stress induced displacements based on said obtained density characteristics data; and corrects the mask layout design data by specifying shift movement of individual photo mask design shapes to pre-compensate for predicted displacements. To obtain data representing density characteristics, the method merges pieces of data that are combined to make a photo mask to obtain a full reticle field data set. The merge includes a merge of data representing density characteristic driven stress effects. The density characteristics data for the merged reticle data are then computed. To predict stress-induced displacements, the method inputs said density characteristics data into a programmed model that predicts displacements as a function of density, and outputs the predicted shift data.

Correcting for stress induced pattern shifts in semiconductor manufacturing

Various embodiments include computer-implemented methods, computer program products and systems for verifying an integrated circuit (IC) layout. In some cases, approaches include a computer-implemented method of verifying an IC layout, the method including: obtaining data about a process variation band for at least one physical feature in the IC layout; determining voltage-based process variation band thresholds for the at least one physical feature in the IC layout; determining whether the process variation band for the at least one physical feature in the IC layout meets design specifications for the IC layout based upon the voltage-based process variation band thresholds for the at least one physical feature in the IC layout; and modifying the IC layout in response to a determination that the process variation band for the at least one physical feature does not meet the design specifications.

Net-voltage-aware optical proximity correction (OPC)

A method of determining focal planes during a photolithographic exposure of a wafer surface is provided. The method may include receiving data corresponding to a surface topography of the wafer surface and determining, based on the received data corresponding to the surface topography, a plurality of regions having substantially different topographies. Reticle design data is received for exposure on the wafer surface, whereby, from the received reticle design data, reticle design data subsets that are each allocated to a corresponding one of the determined plurality of regions are generated. A best fit focal plane is then generated for each of the determined plurality of regions.

Reticle data decomposition for focal plane determination in lithographic processes

In various embodiments, a method of designing an integrated circuit (IC) layout for a multiple patterning layout fill process includes: providing a pre-characterized mask tile library including a plurality of distinct mask tiles each having a distinct mask density on a plurality of distinct exposures each associated with a patterning process in the multiple patterning process; determining a density of a mask group in a first layout window in the IC layout, the first layout window including an open space unfilled by the mask group; and selecting a set of mask tiles from the plurality of distinct mask tiles to fill a portion of the open space, the selecting based upon the determined density of the mask group in the first layout window and the distinct mask density of the selected set of mask tiles on the plurality of distinct exposures.

Density balancing in multiple patterning lithography using integrated circuit layout fill

Embodiments of the present invention provide a method for making mask shape adjustment The method includes creating a first mask shape; identifying one or more mask segments of the first mask shape as candidate mask segments of needing segment adjustment; applying an optical proximity correction (OPC) process to the first mask shape, the OPC process identifying at least one of the candidate mask segments as a constrained mask segment; applying a rotational adjustment to the constrained mask segment; and creating a second mask shape having the constrained mask segment being rotationally adjusted. A system and a machine-readable medium for performing the above method are also provided.

Adjustment of mask shapes for improving printability of dense integrated circuit layout

A solution for performing a data correction on a hierarchical integrated circuit layout is provided. A method includes: receiving a CD compensation map for the long range critical dimension variation prior to the data correction; grouping compensation amounts of the CD compensation into multiple compensation ranges; generating multiple target layers corresponding to the multiple compensation ranges; super-imposing a region of the CD compensation map having a compensation amount falling into a compensation range over a respective target layer to generate a target shape; performing the data correction on the layout to generate a data corrected layout; performing the data correction on the target shape separately to generate a data corrected target shape; and combining the data corrected layout and the data corrected target shape based on the CD compensation map.

Data correcting hierarchical integrated circuit layout accommodating compensate for long range critical dimension variation

An integrated circuit (IC) design method for use as a design and/or manufacturing tool for designing and/or manufacturing integrated circuitry (). The method utilizes one or more library element (A-F) to provide a flexible modeling template. Each library element includes one or more module ports (A-F) each for accepting any one of a plurality of device modules (). The device modules are logical representations of corresponding respective portions of the integrated circuitry. For any given module port, the corresponding device modules may be interchanged essentially without additional integrated circuitry design changes.

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Jeffersonville, VT, United States of America

Ian P Stobert