Microsoft Technology Licensing, LLC

Silicon Graphics, Incorporated

Ian O'Donnell

Carroll Philip Gossett

Vimal S Parikh

Derek Bosch

Eric Demers

Shaun Ho

Adrian Jeday

Ole Bentz

Anan Nagarajan

A processor for computer graphics calculations comprising an entire graphics engine in a single integrated circuit. The processor includes a transform mechanism adapted to compute transforms for the computer graphics calculations. The transform mechanism includes a transformation element adapted to compute transforms using a dot product operation. The transform mechanism of the processor also includes a perspective division element, a color unit for lighting calculations, a scaling element for multiplication operations, and a look-up table containing mathematical functions used by the computer graphics calculations. The processor also includes a raster unit coupled to the transform mechanism, a texture unit coupled to the raster unit, and a shader unit coupled to the texture unit.

Processor for geometry transformations and lighting calculations

An electronic system and method that maintains time dependencies and ordering constraints in an electronic system. A timing controller utilizes a representative bit to track timing dependencies associated with information and ensures the information is communicated and processed in an order that preserves the timing dependencies as the information is converted from parallel to parallel or parallel to serial operations. The present invention tracks the order in which information is loaded in a electronic hardware component and ensures that the information loaded into the electronic hardware component at a particular time is processed without interruption by information loaded at a different time. For example, the timing controller tracks the order in which texel information associated with a pixels parallelly loaded in a staging memory and issues electronic signals that cause the information loaded at a particular time to sequentially empty without interruption by information parallelly loaded in the staging memory at a different time.

TIMING CONTROLLER HAVING DEPENDENCY MEMORY, SELECTION SERIALIZATION COMPONENT AND REORDERING COMPONENT FOR MAINTAINING TIME DEPENDENCIES IN CONVERSIONS BETWEEN SEQUENTIAL AND PARALLEL OPERATIONS USING STAGING MEMORY

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Berkeley, CA, United States of America

Ian O'Donnell