Arm Limited

Ian Michael Caulfield

Peter Richard Greenhalgh

Frederic Claude Marie Piry

Albin Pierrick Tonnerre

Max John Batley

Antony John Penton

Simon John Craske

Allan John Skillman

Alexander Alfred Hornung

Alastair David Reid

Chiloda Ashan Senarath Pathirane

Richard Roy Grisenthwaite

David Raymond Lutz

Thomas Christopher Grocutt

Milosch Meriac

David Hennah Mansell

Yasuo Ishii

Abhishek Raja

Stephan Diestelhorst

Cédric Denis Robert Airaud

Andreas Lars Sandberg

Vladimir Vasekin

Rune Holm

Matthias Lothar Boettcher

Giacomo Gabrielli

Chris Abernathy

Nikos Nikoleris

Michael Alexander Kennedy

Chiloda Ashan Senerath Pathirane

Jelena Milanovic

Anthony Jebson

Timothy Hayes

Dominic Phillip Mulligan

Robert Gwilym Dimond

Thomas Edward Roberts

Andrew James Antony Lees

Nathan Yong Seng Chong

Lei Ma

Jeffrey Allen Kehl

Nathan Young Seng Chong

A data processing apparatus is provided which controls the use of data in respect of a further operation. The data processing apparatus identifies whether data is trusted or untrusted by identifying whether or not the data was determined by a speculatively executed resolve-pending operation. A permission control unit is also provided to control how the data can be used in respect of a further operation according to a security policy while the speculatively executed operation is still resolve-pending.

Controlling use of data determined by a resolve-pending speculative operation

An apparatus supports decoding and execution of a bulk memory instruction specifying a block size parameter. The apparatus comprises control circuitry to determine whether the block size corresponding to the block size parameter exceeds a predetermined threshold, and performs a micro-architectural control action to influence the handling of at least one bulk memory operation by memory operation processing circuitry. The micro-architectural control action varies depending on whether the block size exceeds the predetermined threshold, and further depending on the states of other components and operations within or coupled with the apparatus. The micro-architectural control action could include an alignment correction action, cache allocation control action, or processing circuitry selection action.

Control of bulk memory instructions

An apparatus and method are provided for processing instructions. The apparatus has execution circuitry for executing instructions, where each instruction requires an associated operation to be performed using one or more source operand values in order to produce a result value. Issue circuitry is used to maintain a record of pending instructions awaiting execution by the execution circuitry, and prediction circuitry is used to produce a predicted source operand value for a chosen pending instruction. Optimisation circuitry is then arranged to detect an optimisation condition for the chosen pending instruction when the predicted source operand value is such that, having regard to the associated operation for the chosen pending instruction, the result value is known without performing the associated operation. In response to detection of the optimisation condition, an optimisation operation is implemented instead of causing the execution circuitry to perform the associated operation in order to execute the chosen pending instruction. This can lead to significant performance and/or power consumption improvements.

Apparatus and method for predicting source operand values and optimized processing of instructions

An apparatushas a processing pipelinesupporting at least a first processing mode and a second processing mode with different energy consumption or performance characteristics. A storage structureis accessible in both the first and second processing modes. When the second processing mode is selected, control circuitrytriggers a subsetof the entries of the storage structure to be placed in a power saving state.

Processing pipeline with first and second processing modes having different performance or energy consumption characteristics

An apparatus comprises processing circuitryto perform data processing in response to instructions, the processing circuitry supporting speculative processing of read operations for reading data from a memory system; and control circuitryto identify whether a sequence of instructions to be processed by the processing circuitry includes a speculative side-channel hint instruction indicative of whether there is a risk of information leakage if at least one subsequent read operation is processed speculatively, and to determine whether to trigger a speculative side-channel mitigation measure depending on whether the instructions include the speculative side-channel hint instruction. This can help to reduce the performance impact of measures taken to protect against speculative side-channel attacks.

Speculative side-channel hint instruction

An apparatus for data processing and a method of data processing are provided. Data processing operations are performed in response to instructions which reference architectural registers using physical registers to store data values when performing the data processing operations. Mappings between the architectural registers and the physical registers are stored, and when a data hazard condition is identified with respect to out-of-order program execution of an instruction, an architectural register specified in the instruction is remapped to an available physical register. A reorder buffer stores an entry for each destination architectural register specified by the instruction, entries being stored in program order, and an entry specifies a destination architectural register and an original physical register to which the destination architectural register was mapped before the architectural register remapped to an available physical register.

Apparatus and method for supporting out-of-order program execution of instructions

An apparatus and method of operating a data processing apparatus are disclosed. The apparatus comprises data processing circuitry to perform data processing operations in response to a sequence of instructions, wherein the data processing circuitry is capable of performing speculative execution of at least some of the sequence of instructions. A cache structure comprising entries stores temporary copies of data items which are subjected to the data processing operations and speculative execution tracking circuitry monitors correctness of the speculative execution and responsive to indication of incorrect speculative execution to cause entries in the cache structure allocated by the incorrect speculative execution to be evicted from the cache structure.

Tracking speculative data caching

Examples of the present disclosure relate to an apparatus comprising execution circuitry to execute instructions defining data processing operations on data items. The apparatus comprises cache storage to store temporary copies of the data items. The apparatus comprises prefetching circuitry to a) predict that a data item will be subject to the data processing operations by the execution circuitry by determining that the data item is consistent with an extrapolation of previous data item retrieval by the execution circuitry, and identifying that at least one control flow element of the instructions indicates that the data item will be subject to the data processing operations by the execution circuitry; and b) prefetch the data item into the cache storage.

Apparatus and method for prefetching data items

An apparatus and method are provided for controlling allocation of instructions into an instruction cache storage. The apparatus comprises processing circuitry to execute instructions, fetch circuitry to fetch instructions from memory for execution by the processing circuitry, and an instruction cache storage to store instructions fetched from the memory by the fetch circuitry. Cache control circuitry is responsive to the fetch circuitry fetching a target instruction from a memory address determined as a target address of an instruction flow changing instruction, at least when the memory address is within a specific address range, to prevent allocation of the fetched target instruction into the instruction cache storage unless the fetched target instruction is at least one specific type of instruction. It has been found that such an approach can inhibit the performance of speculation-based caching timing side-channel attacks.

Apparatus and method for controlling allocation of instructions into an instruction cache storage

Techniques for performing matrix multiplication in a data processing apparatus are disclosed, comprising apparatuses, matrix multiply instructions, methods of operating the apparatuses, and virtual machine implementations. Registers, each register for storing at least four data elements, are referenced by a matrix multiply instruction and in response to the matrix multiply instruction a matrix multiply operation is carried out. First and second matrices of data elements are extracted from first and second source registers, and plural dot product operations, acting on respective rows of the first matrix and respective columns of the second matrix are performed to generate a square matrix of result data elements, which is applied to a destination register. A higher computation density for a given number of register operands is achieved with respect to vector-by-element techniques.

Register-based matrix multiplication with multiple matrices per register

Coherency control circuitry () supports processing of a safe-speculative-read transaction received from a requesting master device (). The safe-speculative-read transaction is of a type requesting that target data is returned to a requesting cache () of the requesting master device () while prohibiting any change in coherency state associated with the target data in other caches () in response to the safe-speculative-read transaction. In response, at least when the target data is cached in a second cache associated with a second master device, at least one of the coherency control circuitry () and the second cache () is configured to return a safe-speculative-read response while maintaining the target data in the same coherency state within the second cache. This helps to mitigate against speculative side-channel attacks.

Cache control in presence of speculative read operations

A data processing apparatus comprises branch prediction circuitry adapted to store at least one branch prediction state entry in relation to a stream of instructions, input circuitry to receive at least one input to generate a new branch prediction state entry, wherein the at least one input comprises a plurality of bits; and coding circuitry adapted to perform an encoding operation to encode at least some of the plurality of bits based on a value associated with a current execution environment in which the stream of instructions is being executed. This guards against potential attacks which exploit the ability for branch prediction entries trained by one execution environment to be used by another execution environment as a basis for branch predictions.

Encoding of input to storage circuitry

A processing pipeline may have first and second execution circuits having different performance or energy consumption characteristics. Instruction supply circuitry may support different instruction supply schemes with different energy consumption or performance characteristics. This can allow a further trade-off between performance and energy efficiency. Architectural state storage can be shared between the execute units to reduce the overhead of switching between the units. In a parallel execution mode, groups of instructions can be executed on both execute units in parallel.

Apparatus and branch prediction circuitry having first and second branch prediction schemes, and method

Processing circuitry includes execute circuitry for executing micro-operations in response to instructions fetched from a data store. Control circuitry is provided to determine, based on availability of at least one processing resource, how many micro-operations are to be executed by the execute circuitry in response to a given set of one or more instructions fetched from the data store.

Execution of micro-operations

An apparatus comprises a cache memory to store data as a plurality of cache lines each having a data size and an associated physical address in a memory, access circuitry to access the data stored in the cache memory, detection circuitry to detect, for at least a set of sub-units of the cache lines stored in the cache memory, whether a number of accesses by the access circuitry to a given sub-unit exceeds a predetermined threshold, in which each sub-unit has a data size that is smaller than the data size of a cache line, prediction circuitry to generate a prediction, for a given region of a plurality of regions of physical address space, of whether data stored in that region comprises streaming data in which each of one or more portions of the given cache line is predicted to be subject to a maximum of one read operation or multiple access data in which each of the one or more portions of the given cache line is predicted to be subject to more than one read operation, the prediction circuitry being configured to generate the prediction in response to a detection by the detection circuitry of whether the number of accesses to a sub-unit of a cache line having an associated physical address in the given region exceeds the predetermined threshold, and allocation circuitry to selectively allocate a next cache line to the cache memory in dependence upon the prediction applicable to the region of physical address space containing that next cache line.

Growing community of inventors

Cambridge, United Kingdom

Ian Michael Caulfield