Intel Corporation

Ian M Steiner

Krishnakanth Venkata Sistla

Ankush Varma

Vivek Garg

Matthew M Bace

Avinash N Ananthakrishnan

Nikhil Gupta

Martin Rowland

Corey D Gough

Ripan Das

Efraim Rotem

Eliezer Weissmann

Jason W Brandt

Stephen H Gunther

Andrew J Herdrich

Alon Naveh

John Joseph Browne

Jeremy J Shrall

Chris MacNamara

Vasudevan Srinivasan

Anil Aggarwal

Nagasubramanian Gurumoorthy

Venkatesh Ramamurthy

William Johnson Bowhill

Sujal A Vora

David P Lerner

Joseph M Sullivan

Tessil Thomas

Kai Cheng

Jonathan M Eastep

Federico Ardanaz

Devadatta V Bodas

James W Alexander

Eric J DeHaemer

Reid James Riedlinger

Arijit Biswas

Son H Lam

Chris Poirier

Daniel G Borkowski

Mark Rowland

Buck Gremel

Leeor Peled

Krishna Kant

Eric Dehaemer

Allen W Chu

Asma Al-Rawi

Lokesh Sharma

Michael Prinke

Robert Valentine

David M Durham

Kshitij Arun Doshi

Ravi L Sahita

Mohan J Kumar

Baiju V Patel

Ravishankar Iyer

Michael Lemay

Sara S Baghsorkhi

Alexander Gendler

Jr-Shian Tsai

Vadim Sukhomlinov

Alexander Bachmutsky

Mingqiu Sun

Ramamurthy Krithivas

Richard J Greco

Jeffrey D Chamberlain

Malini Krishnan Bhandaru

Eric Dahlen

Nilesh K Jain

Mohammad R Haghighat

Mingwei Zhang

Scott P Bobholz

Zhong-Ning George Cai

Amin Firoozshahian

Phani Kumar Kandula

Yeluri Raghuram

Gavri Berger

Dmitry Babokin

Anil Rao

Krishna Bhuyan

Ameya Ambardekar

Krishnamurthy Jambur Sathyanarayana

Saurabh Tiwari

Shmuel Zobel

Eyal Hadas

Howard Chin

Edo Hachamo

Wenhui Shu

Micah Barany

Gopikrishna Jandhyala

Teck Joo Goh

Areg Melik-Adamyan

Harshad S Sane

Jeffrey S Wilder

A Leonard Brown

Sumesh Subramanian

Anup Mohan

Eylon Toledano

Chelsea Akturan

Cagdas Akturan

Dianjun Sun

A processing device includes a plurality of processing cores, a control register, associated with a first processing core of the plurality of processing cores, to store a first base clock frequency value at which the first processing core is to run, and a power management circuit to receive a base clock frequency request comprising a second base clock frequency value, store the second base clock frequency value in the control register to cause the first processing core to run at the second base clock frequency value, and expose the second base clock frequency value on a hardware interface associated with the power management circuit.

Configuration of base clock frequency of processor based on usage parameters

Embodiments of systems, apparatuses and methods provide enhanced function as a service (FaaS) to users, e.g., computer developers and cloud service providers (CSPs). A computing system configured to provide such enhanced FaaS service include one or more controls architectural subsystems, software and orchestration subsystems, network and storage subsystems, and security subsystems. The computing system executes functions in response to events triggered by the users in an execution environment provided by the architectural subsystems, which represent an abstraction of execution management and shield the users from the burden of managing the execution. The software and orchestration subsystems allocate computing resources for the function execution by intelligently spinning up and down containers for function code with decreased instantiation latency and increased execution scalability while maintaining secured execution. Furthermore, the computing system enables customers to pay only when their code gets executed with a granular billing down to millisecond increments.

Function as a service (FaaS) system enhancements

In one embodiment, a processor includes at least one core to execute instructions, one or more thermal sensors associated with the at least one core, and a power controller coupled to the at least one core. The power controller has a control logic to receive temperature information regarding the processor and dynamically determine a maximum allowable average power limit based at least in part on the temperature information. The control logic may further maintain a static maximum base operating frequency of the processor regardless of a value of the temperature information. Other embodiments are described and claimed.

Controlling average power limits of a processor

Examples include a computing system for receiving memory class of service parameters; setting performance monitoring configuration parameters, based at least in part on the memory class of service parameters, for use by a performance monitor of a memory controller to generate performance monitoring statistics by monitoring performance of one or more workloads by a plurality of processor cores based at least in part on the performance monitoring configuration parameters; receiving the performance monitoring statistics from the performance monitor; and generating, based at least in part on the performance monitoring statistics, a plurality of memory bandwidth settings to be applied by a memory bandwidth allocator to the plurality of processor cores to dynamically adjust priorities of memory bandwidth allocated for the one or more workloads to be processed by the plurality of processor cores.

Dynamic control of memory bandwidth allocation for a processor

In one embodiment, a processor includes a current protection controller to: receive instruction width information and instruction type information associated with one or more instructions stored in an instruction queue prior to execution of the one or more instructions by an execution circuit; determine a power license level for the core based on the corresponding instruction width information and the instruction type information; generate a request for a license for the core corresponding to the power license level; and communicate the request to a power controller when the one or more instructions are non-speculative, and defer communication of the request when at least one of the one or more instructions is speculative. Other embodiments are described and claimed.

System, apparatus and method for power license control of a processor

A multicore processor may include multiple processing cores that were previously designated as active cores and at least one processing core that was previously designated as a functional spare. The processor may include an interface to receive, during operation of the processor in an end-user environment, a request to change the designation of at least one of the processing cores. The processor may be to store, into a desired cores configuration data structure in response to the request, data representing a bitmask that reflects the requested change, and to execute a reset sequence. During the reset sequence, the processor may activate, dependent on the bitmask, a processing core previously designated as a functional spare, or may deactivate, dependent on the bitmask, a processing core previously designated as an active core. The processor may include a predetermined maximum number of active cores and a predetermined minimum number of functional spares.

Systems and methods for in-field core failover

Various embodiments comprise prioritizing frequency allocations in thermally- or power-constrained computing devices. Computer elements may be assigned 'weights' based on their priorities. The computer elements with higher weights may receive higher frequency allocations to assure they receive priority in processing more quickly. The computer elements with lower weights may receive lower frequency allocations and suffer a slowdown in their processing. Elements with the same weight may be grouped together for the purpose of frequency allocation.

Hybrid prioritized resource allocation in thermally-or power-constrained computing devices

A simultaneous multi-threading (SMT) processor core capable of thread-based biasing with respect to execution resources. The SMT processor includes priority controller circuitry to determine a thread priority value for each of a plurality of threads to be executed by the SMT processor core and to generate a priority vector comprising the thread priority value of each of the plurality of threads. The SMT processor further includes thread selector circuitry to make execution cycle assignments of a pipeline by assigning to each of the plurality of threads a portion of the pipeline's execution cycles based on each thread's priority value in the priority vector. The thread selector circuitry is further to select, from the plurality of threads, tasks to be processed by the pipeline based on the execution cycle assignments.

Apparatus, method, and system for ensuring quality of service for multi-threading processor cores

Hybrid prioritized resource allocation in thermally- or power-constrained computing devices

A method is provided for controlling a link. This may include determining a condition of a first device coupled to the link, receiving, at the first device, a request for a specific link state from a second device coupled to the link, and determining a power state of the link based on the determined condition of the first device.

Method and apparatus to control a link power state

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Hillsboro, OR, United States of America

Ian M Steiner