Texas Instruments Corporation

Ian Lloyd Bower

Zhaofu Zhou

Hua Tang

Teng Feng

Shanguang Xu

Craig Lance Dalley

Ching-Yuh Tsay

John D Provence

Richard E Downing

George Paul Eaves

Paul Eaves

Yunsheng Qu

In at least one example, an apparatus includes a current sense circuit, an imbalance detector, and a current balancer. The current sense circuit including a first phase input, a second phase input, a first sense output, and a second sense output. The imbalance detector having a detector output, a first detector input, and second detector input. The first detector input is coupled to the first sense output and the second detector input is coupled to the second sense output. The current balancer having a balancer input and a balancer output. The balancer input is coupled to the detector output.

Interleaved phase current balancing

An example apparatus includes: a first and second capacitor; a first and second inductor; a first switch having a first and second terminal, the first terminal coupled to the first capacitor, and the second terminal coupled to the first and second inductor; a second switch having a third and fourth terminal, the third terminal coupled to the second terminal, the fourth terminal coupled to the second capacitor; a third switch having a fifth and sixth terminal, the fifth terminal coupled to the first terminal, the sixth terminal coupled to the second inductor; and a diode having a seventh and eighth terminal, the seventh terminal coupled to the sixth terminal, the eighth terminal coupled to the fourth terminal.

Methods and apparatus to reduce reverse recovery during the operation of an inverting buck boost converter

A DC-DC converter includes a ramp generator, a threshold voltage circuit, and a control circuit. The ramp generator is configured to generate a voltage ramp. The threshold voltage circuit is configured to generate a threshold voltage. The control circuit is coupled to the ramp generator and the threshold voltage circuit. The control circuit includes a digital pulse width modulator (DPWM) circuit and a loop compensation circuit coupled to the DPWM circuit. The DPWM circuit is configured to generate a power stage switch control signal responsive to a loop compensation value. The loop compensation circuit is coupled to the DPWM circuit. The loop compensation circuit is configured to calculate the loop compensation value responsive to the voltage ramp exceeding the threshold voltage.

DC-DC converter with mode-switching compensation loop

A mixed-signal processor (MSP) chip with a flexible serial interface which simultaneously accommodates two serial ports on a reduced number of pins. The pin definitions of these serial ports are configured to function well with several different external chips. Any two of these chips, or two of any one of these chips, may be used concurrently by the present MSP. When used with chips that require it, the present MSP chip provides a clock signal to each of these. When used with other chips, the MSP will can receive a clock signal from an external chip, and will then pass this signal through to any chip on the other of the two serial ports.

Innovative dual-channel serial interface circuit scheme

A computing device (10) includes a processor (14) coupled to a memory interface (28). The memory interface (28) supports access to a variety of memories (12) using at least two different data lengths. The memory interface (28) includes an address register (50, 52) for receiving addressing information to access the memory (12). A mode bit (80) and a high/low bit (82) in the address register (50, 52) determine the different operating modes of the memory interface (28).

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Dallas, TX, United States of America

Ian Lloyd Bower