Snap Inc.

Lsi Logic Corporation

Ian Kyles

Edmund Passon

Howard V Goetz

Glen Sands

Nicholas William Melena

Joshua T Wiersma

Aaron Boyce

Jamie J LeVasseur

Rock Edward Kent

Patrick R Thornton

Clive David Beech

Tyson Heskett

Trent D Whitten

Jean-Marc Patenaude

Fernando Y Chen

Mark E Haisch

A method is disclosed for controlling a liquid crystal pulse width modulated display. A repetition period includes A group periods, each including B modulation intervals, each modulation interval spanning H unit durations and, except for the final modulation interval of the repetition period, a remainder unit duration. A desired number N of unit duration pulses are distributed into H unit duration pulses for each modulation interval, with remainder desired pulses distributed among the remainder unit durations of the modulation intervals. A drive sequence is generated, including one or more repetitions of the repetition period.

Pulse width modulation for phase-modulating display

A system of the present invention reduces the size and/or increases the efficiency of a display system or device that integrates or includes a display, for example, an LED display such as a microLED display and OLED display or an LCoS display into such system or device. Embodiments of the present disclosure include, but are not limited to, a display wherein the at least two pixels are four pixels comprising two green pixels, one blue pixel, and one red pixel, and wherein a pixel logic circuit maintains the red pixel in an on state while driving the two green pixels and the blue pixel in accordance with a field sequential color (FSC) pixel drive process or method.

System and method for driving a pixel with optimized power and area

Systems and methods for varying an intensity of pixels of displays are provided. A display subsystem may include a display driver for receiving image frame data and commands from an image or data source, including pixel intensity values for bit planes of an image frame; a parser for receiving the image frame data and the commands, and configured to determine a drive waveform having an pixel drive value and a pixel drive time interval for each bit plane of the image frame data; a display backplane for receiving the drive waveform, the display backplane including a pixel array comprising an array of pixels, each pixel driven by a pixel circuit; and display driver circuitry for driving the pixels in accordance with the drive waveform; and wherein an intensity of the pixel varies for each bit plane according to the pixel drive value and the pixel drive time interval.

Systems and methods of driving a display with high bit depth

Systems, methods, apparatuses and devices provide an integrated display module or apparatus including a Liquid crystal assembly with highly integrated components including display driver circuitry and backplane circuitry. These approaches provide for packaging of displays with small form-factor displays and microdisplays and, in aspects, for usage in virtual and augmented reality devices.

Integrated display module or apparatus and methods for operating and manufacturing the same

Updating an image displayed on a display device. The display device includes pixels in a pixel array. A system comprising a display subsystem for executing commands and displaying images, said display subsystem comprising a parser for receiving the image frame data, wherein the parser extracts updated image data and the commands. The system includes a storage device for storing the updated image data in a updated cache location according to the commands. The system includes a loader for reading the commands to identify and fetch the updated image data from the storage device. The system includes display backplane circuitry for receiving the updated image data from the loader and for updating pixel driver circuity for pixels within the updated image data. The embodiments herein can be used for driving micro-displays such as LCoS micro-LED displays.

Updating an image displayed on a display device

Displays, systems, and methods may be utilized in applications including, but not limited to, projectors, head-up displays, and augmented reality (AR), mixed reality (MR), and virtual reality (VR) systems or devices, such as headsets or other near-eye devices or systems. Tiled or Tile-able displays and methods, in accordance with the present invention, provide displays of varying sizes, and as such, a Tiled or Tile-able display is configured to accommodate the display size needed for various wearable and mobile devices that require or incorporate displays.

Systems and methods for configuring a display device and display system

A system for updating an image on a display device includes pixels in a pixel array. The system includes a display subsystem for executing commands and displaying images, the display subsystem also includes a parser for receiving image frame data, and extracting updated image data and commands. A storage device is used for storing the updated image data in an updated cache location according to the commands. A loader is used for reading the commands to identify and fetch the updated image data from the storage device. Display backplane circuitry is used for receiving the updated image data from the loader and for updating pixel driver circuity for pixels within the updated image data. The examples described are ideal for driving micro-displays such as LCoS micro-LED displays.

Systems and methods for updating an image displayed on a display device

A clock and data recovery circuit for use in a serial data communications channel includes two phase-locked loops, the two PLLs being coupled together through the use of a matched pair of voltage controlled oscillators. Each of the matched pair of oscillators includes both coarse and fine adjustment inputs. The first loop generates a first frequency based upon a reference clock input and provides a coarse tuning signal, based on the first frequency, to the second loop circuit. The second VCO drives the second loop circuit at the same frequency as the first circuit, while the second circuit is also coupled to the incoming data stream so as to provide the fine adjustment input to the second VCO. In this way, the second VCO, i.e., the second loop, is synchronized to the data, yet it remains synchronized to the reference frequency even during relatively long periods of time during which transitions in the data stream are infrequent.

Dual-loop clock and data recovery for serial data communication

A circuit and method are shown for a continuously adjustable delay circuit. The present invention utilizes two signal delay paths controlled by a tuning signal wherein each delay path receives a reference signal. The first delay path delays the reference signal in response to the tuning signal in a manner that is complementary to the manner in which the second delay path delays the reference signal in response to the tuning signal. By selecting one of the signal output by the first delay path and the signal output by the second delay path and switching between the two signals at a point when the two signals are separated by a period of the reference signal, a delay of the reference signal can be continuously adjusted.

Growing community of inventors

West Linn, OR, United States of America

Ian Kyles