Nvidia Corporation

Ian Kwong

John Matthew Burgess

Samuli Matias Laine

Timo Oskari Aila

Tero Tapani Karras

William P Newhall, Jr

Robert Ohannessian

Greg Muthler

Gregory Muthler

Magnus Andersson

Peter Michael Nelson

Edward Biddulph

Peter Nelson

Techniques applicable to a ray tracing hardware accelerator for traversing a hierarchical acceleration structure with reduced false positive ray intersections are disclosed. The reduction of false positives may be based upon one or more of selectively performing a secondary higher precision intersection test for a bounding volume, identifying and culling bounding volumes that degenerate to a point, and parametrically clipping rays that exceed certain configured distance thresholds.

Reducing false positive ray traversal in a bounding volume hierarchy

Reducing false positive ray traversal using point degenerate culling

Reducing false positive ray traversal using ray clipping

A hardware-based traversal coprocessor provides acceleration of tree traversal operations searching for intersections between primitives represented in a tree data structure and a ray. The primitives may include triangles used in generating a virtual scene. The hardware-based traversal coprocessor is configured to properly handle numerically challenging computations at or near edges and/or vertices of primitives and/or ensure that a single intersection is reported when a ray intersects a surface formed by primitives at or near edges and/or vertices of the primitives.

Watertight ray triangle intersection

Growing community of inventors

San Jose, CA, United States of America

Ian Kwong