Seagate Technology Incorporated

Ian James Gilbert

Jon David Trantham

Praveen Viraraghavan

Mohamad H El-Batal

John West Dykes

Darshana H Mehta

Matthew J Totin

Sangita Shreedharan Kalarickal

Tim Rausch

Peng Peng

Jan-Ulrich Thiele

Todd Michael Lammers

Walter Richard Eppler

Drew Michael Mader

Steven Douglas Granz

Method and apparatus for managing a front-end cache formed of ferroelectric memory element (FME) cells. Prior to storage of writeback data associated with a pending write command from a client device, an intelligent cache manager circuit forwards a first status value indicative that sufficient capacity is available in the front-end cache for the writeback data. Non-requested speculative readback data previously transferred to the front-end cache from the main NVM memory store may be jettisoned to accommodate the writeback data. A second status value may be supplied to the client device if insufficient capacity is available to store the writeback data in the front-end cache, and a different, non-FME based cache may be used in such case. Mode select inputs can be supplied by the client device specify a particular quality of service level for the front-end cache, enabling selection of suitable writeback and speculative readback data processing strategies.

Intelligent management of ferroelectric memory in a data storage device

Apparatus and method for managing data in a non-volatile memory (NVM) having an array of ferroelectric memory cells (FMEs). A data set received from an external client device is programmed to a group of the FMEs at a target location in the NVM using a selected profile. The selected profile provides different program characteristics, such as applied voltage magnitude and pulse duration, to achieve desired levels of power used during the program operation, endurance of the data set, and latency effects associated with a subsequent read operation to retrieve the data set. The profile may be selected from among a plurality of profiles for different operational conditions. The ferroelectric NVM may form a portion of a solid-state drive (SSD) storage device. Different types of FMEs may be utilized including ferroelectric tunneling junctions (FTJs), ferroelectric random access memory (FeRAM), and ferroelectric field effect transistors (FeFETs).

Balancing power, endurance and latency in a ferroelectric memory

A system on chip (SOC) integrated circuit device having an incorporated ferroelectric memory configured to be selectively refreshed, or not, depending on different operational modes. The ferroelectric memory is formed of an array of ferroelectric memory elements (FMEs) characterized as non-volatile, read-destructive semiconductor memory cells each having at least one ferroelectric layer. The FMEs can include FeRAM, FeFET or FTJ constructions. A read/write circuit writes data to the FMEs and subsequently reads back data from the FMEs responsive to respective write and read signals supplied by a processor circuit of the SOC. A refresh circuit is selectively enabled in a first normal mode to refresh the FMEs after a read operation, and is selectively disabled in a second exception mode so that the FMEs are not refreshed after a read operation. The FMEs can be used as a main memory, a cache, a buffer, an OTP, a keystore, etc.

System on chip (SOC) with processor and integrated ferroelectric memory

A data storage system can utilize one or more data storage devices that employ a solid-state non-volatile read destructive memory consisting of ferroelectric memory cells. A leveling strategy can be generated by a wear module connected to the memory with the leveling strategy prescribing a plurality of memory cell operating parameters associated with different amounts of cell wear. The wear module may monitor activity of a memory cell and detect an amount of wear in the memory cell as a result of the monitored activity, which can prompt changing a default set of operating parameters for the memory cell to a first stage of operating parameters, as prescribed by the leveling strategy, in response to the detected amount of wear.

Read destructive memory wear leveling system

A non-volatile memory (NVM) is formed of memory cells each having multiple ferroelectric memory elements (FMEs). Each FME stores data in relation to an electrical polarity of a recording layer formed of ferroelectric or anti-ferroelectric material. Each multi-FME memory cell is coupled to a set of external control lines activated by a control circuit in a selected order to perform program and/or read operations upon the FMEs. The FMEs may share a nominally identical construction or may have different constructions. Data are programmed and written responsive to the respective program/read responses of the FMEs. Constructions can include ferroelectric tunneling junctions (FTJs), ferroelectric random access memory (FeRAM), and ferroelectric field effect transistors (FeFETs). The NVM may form a portion of a data storage device, such as a solid-state drive (SSD).

Non-volatile memory cell with multiple ferroelectric memory elements (FMEs)

Apparatus and method for managing data in a processing system, such as but not limited to a data storage device such as a solid-state drive (SSD). A ferroelectric stack register memory has a first arrangement of ferroelectric memory cells (FMEs) of a first construction and a second arrangement of FMEs of a different, second construction arranged to provide respective cache lines for use by a controller, such as a programmable processor. A pointer mechanism is configured to provide pointers to point to each of the respective cache lines based on a time sequence of operation of the processor. Data sets can be migrated to the different arrangements by the controller as required based on the different operational characteristics of the respective FME constructions. The FMEs may be non-volatile and read-destructive. Refresh circuitry can be selectively enacted under different operational modes.

Stack register having different ferroelectric memory element constructions

A memory device formed of ferroelectric field effect transistors (FeFETs). The memory device can be used as a front end buffer, such as in a data storage device having a non-volatile memory (NVM). A controller can be configured to transfer user data between the NVM and an external client (host) via the buffer. The FeFETs can be arranged in a two-dimensional (2D) or a three-dimensional (3D) array. A monitor circuit can be used to monitor operation of the FeFETs. An optimization controller can be used to adjust at least one operational parameter associated with the FeFETs responsive to the monitored operation by the monitor circuit. The FeFETs may require a refresh operation after each read operation. A power down sequence can involve a read operation without a subsequent refresh operation to wipe the FeFETs, the read operation jettisoning the data read from the buffer memory.

Front end buffer having ferroelectric field effect transistor (FeFET) based memory

A data storage system can employ a read destructive memory configured to fill a first cache with a first data set from a data repository prior to populating a second cache with a second data set describing the first data set with the first and second cache each having non-volatile ferroelectric memory cells. An entirety of the first cache may be read in response to a cache hit in the second cache with the cache hit responsive to a data read command from a host and with the first cache being read without a refresh operation restoring the data of the first cache.

Intelligent cache with read destructive memory cells

A data storage system can employ a read destructive memory configured with multiple levels. A non-volatile memory unit can be programmed with a first logical state in response to a first write voltage of a first hysteresis loop by a write controller prior to being programmed to a second logical state in response to a second write voltage of the first hysteresis loop, as directed by the write controller. The first and second logical states may be present concurrently in the non-volatile memory unit and subsequently read concurrently as the first logical state and the second logical state.

Data storage with multi-level read destructive memory

A data storage medium includes a substrate, and a plurality of spaced-apart discrete data storage tracks supported by the substrate. The data storage medium also includes magnetic flux sinking material between the discrete data storage tracks and over the substrate. As an alternative to the magnetic flux sinking material, plasmonic material may be included between the discrete data storage tracks and over the substrate.

Discrete track magnetic recording for EAMR

Two or more different recording currents are applied to a write coil of a recording head. A first of the two or more currents is a positive current and a second of the two or more currents is a negative current. In response to the application of the two or more different recording currents, a data stream is recorded to regions of a moving continuous magnetic recording medium such that each region has three or more magnetic states. The three or more magnetic states can be read from the continuous magnetic recording medium via a magnetic read transducer to recover the data stream.

Method and apparatus for magnetically recording data with three or more states per unit of data

A disk drive apparatus determines a pattern of bits of a data signal applied to a magnetic write transducer of a heat-assisted magnetic recording apparatus. The magnetic write transducer applies a magnetic field to a recording medium in response to the data signal. A laser power signal is applied to a laser that heats the recording medium while the magnetic field is applied. The laser power signal is modulated based on the pattern of bits. The modulation reduces differences between track widths of recorded marks having different elapsed time values and/or increases a signal-to-noise ratio of the recorded marks having different elapsed time values.

Method and apparatus for modulating a laser power signal during heat-assisted magnetic recording

Two or more different elapsed time values are determined between transitions of a data signal applied to a magnetic write transducer of a heat-assisted magnetic recording apparatus. Two or more different power values of the laser are respectively associated with the two or more different elapsed time values. The two or more different power levels are selected to reduce differences between track widths of recorded marks having the two or more different elapsed time values.

Heat-assisted magnetic recording apparatus that modulates laser power to reduce differences between track widths of recorded marks

Pseudorandom bit sequences are recorded to a heat-assisted recording medium at a laser power that is stepped while recording the pseudorandom bit sequences. The pseudorandom bit sequences are read from the heat-assisted recording medium to determine timing differences between bits written before and after the laser power is stepped. A thermal gradient of bits written to the heat-assisted recording medium is determined based on the timing differences.

Growing community of inventors

Chanhassen, MN, United States of America

Ian James Gilbert