Cadence Design Systems, Inc.

Ian Gebbie

Donald John O'Riordan

Keith Dennison

Amit Chopra

Zsolt Haag

Sumit Arora

Jean-Daniel Sonnard

Ian Campbell Dennison

John Purchase

An improved approach is provided to displaying waveform data, where a schematic and corresponding waveform data can be displayed directly on a schematic of an electronic circuit. By providing both the schematic and waveform results in a same display, circuit designers and verification engineers are given more control over their working environments and can more efficiently utilize available data including the schematic and the waveform data. Furthermore, results can be pinned to a relevant net to which those results correspond providing circuit designers and verification engineers with an ability to view only the available data they wish to view, and to do so in a context of the electronic circuit itself on the schematic.

Method and system for displaying waveform results directly on a schematic

Features are provided for graphically representing constraints on design objects in an Electronic Design Automation tool. A particular constraint on one or more circuit objects is displayed as a highlighted region that extends to each visible circuit object to which the constraint applies. Attributes of the highlighted region, such as density and thickness, may proportionally represent attributes of the constraint, such as a strength or distance specified by the constraint. The highlighted region is superimposed on or around circuit objects. The highlighted region may be a halo, which is a partially transparent region filled with a color. Multiple regions that represent the same type of constraint or relationship are connected by line segments, providing the ability to visualize groups of constrained objects, including groups that span levels of a hierarchical design. Intersecting highlighted regions are blended together using techniques such as alpha blending.

System and method for improved visualization and debugging of constraint circuit objects

A method, mechanism, and system for determining an effective resistance for a network of resistors, irrespective of the number of terminals is provided. An aspect of an approach relates to the reduction of any network of resistors to a single resistance value. Another aspect of an approach relates to the application of a power loss calculation to determine the effective resistance. Yet another aspect of an approach relates to the integration of the method/mechanism with an analog simulator.

Method and system for performing effective resistance calculation for a network of resistors

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Edinburgh, United Kingdom

Ian Gebbie