Arm Limited

Ian Field

Paul Kimelman

Edmond John Simon Ashfield

Steven Richard Mellor

Richard Roy Grisenthwaite

Andrew Brookfield Swaine

Thomas Sean Houlihane

David Francis McHale

Simon Axford

Man Cheung Joseph Yiu

Gary Campbell

Nicholas Esca Smith

Cédric Airaud

A direct memory access controller for controlling data transfer between a plurality of data sources and a plurality of data destinations is disclosed. The plurality of data sources and data destinations communicate with the direct memory access controller via a plurality of channels, the direct memory access controller further communicates with a memory and a processor. The memory stores two sets of control data for each of the plurality of channels and for the processor. The direct memory access controller is responsive to a data transfer request received from one of said plurality of channels or from said processor to access one set of said corresponding control data stored in said memory, said direct memory access performing at least a portion of said data transfer requested in dependence upon said accessed control data.

Controlling complex non-linear data transfers

An interrupt controller and method are provided for handling interrupt requests generated by a plurality of interrupt sources. The interrupt controller comprises pend logic for receiving interrupt requests generated by the plurality of interrupt sources, and for each interrupt request, determining whether to accept that interrupt request for handling by the interrupt controller. Interrupt handling logic then selects an interrupt request from amongst those interrupt requests accepted by the pend logic, and generates an indication of the interrupt routine to be executed by a processor to process that interrupt request. The pend logic is arranged, for each of the interrupt sources, to detect a transition of the associated interrupt request from an unset state to a set state, and to accept the interrupt request upon such detection. The pend logic also receives an exit signal indicating completion of the interrupt routine by the processor, and if the associated interrupt request is in the set state on receipt of the exit signal, re-accepts that interrupt request. By such an approach, the interrupt controller can automatically support both level interrupt requests and pulsed interrupt requests without the need for software configuration.

Interrupt controller and method for handling interrupts

A data processing systemsupporting interrupt handling is provided with an interrupt controller. The interrupt controller is responsive to save state data when interrupt processing is commenced by pre-emption of existing processing, whether that be background processing or another interrupt. If a further interrupt is required to be executed immediately after the interrupt which triggered the pre-emption, then the speed with which interrupt processing can be started is advantageously increased if that subsequent interrupt processing is performed without restoring and then resaving the original state data. The interrupts in this arrangement can be considered to be chained together without intervening save and restore operations.

Interrupt processing control

An integrated circuit having a plurality of functional circuits interconnected via a functional bus is provided with a diagnostic bus-master circuit which uses bus transactions on the functional bus to perform diagnostic operations. These diagnostic operations can be performed in real time during normal speed operation of the integrated circuit to produce more accurate diagnostic results. The diagnostic bus-master circuit is particularly useful for reading data values from memory or writing data values to memory as part of diagnostic operations.

On-board diagnostic circuit for an integrated circuit

An integrated circuit is provided with diagnostic circuitry, such as serial scan chains or debug bus access circuits, with which communication is established using an interface circuit coupled with a bi-directional serial link to an external diagnostic device. The bi-directional serial link carries both data and control signals.

Communication interface for diagnostic circuits of an integrated circuit

An integrated circuit is provided with a diagnostic data capture and output system in the form of a diagnostic data capture circuit which captures a data word and a context word from a bus. The bus may be the functional bus connecting functional circuits within the integrated circuit or a dedicated bus linking one or more functional circuits directly to the diagnostic data capture circuit. The diagnostic data captured is buffered within a first-in-first-out buffer and then serialised for output. The diagnostic data fields also include a time value indicative of the time at which the diagnostic data field concerned was captured and whether any diagnostic data fields have failed to be captured.

Diagnostic data capture within an integrated circuit

A method and data processing apparatus for remapping selected data access requests issued by a processor for accessing data items stored on a ROM. The method comprises the following steps: storing at least one replacement data item corresponding to at least one data item and different to said at least one data item in a portion of a RAM memory block, said RAM memory block being accessible by said processor, and said portion having been defined for storage of said at least one replacement data item; intercepting a data access request from said processor to said ROM; comparing at least a portion of an address of said intercepted data access request with a stored at least one identifier, said stored at least one identifier identifying an address of at least one data item stored on said ROM, and depending on said comparison either: remapping said data access request to said RAM memory block, such that a replacement data item stored on said memory block is accessed if said comparison indicates said at least a portion of an address to correspond to an address identified by said at least one identifier; or if said comparison indicates said at least a portion of an address not to be an address identified by said at least one stored identifier accessing a data item located at a position corresponding to said address on said ROM.

Method and apparatus for using a RAM memory block to remap ROM access requests

A data processing systemhaving a nested interrupt controllersupports nested active interrupts. The priority levels associated with different interrupts are alterable (possibly programmable) whilst the system is running. In order to prevent problems associated with priority inversions within nested interrupts, the nested interrupt controller when considering whether a pending interrupt should pre-empt existing active interrupts, compares the priority of the pending interrupt with the highest priority of any of the currently active interrupts that are nested together.

Interrupt priority control within a nested interrupt system

An integrated circuit including diagnostic circuitry having serial scan chains or debug bus access circuits for establishing communication using an interface circuit coupled with a bi-directional serial link to an external diagnostic device. The bi-directional serial link carries both data and control signals. The serial protocol provides for a pacing signal for indicating to the external diagnostic device when it is ready to receive more data and/or when it has completed a particular diagnostic operation. This provides a self-pacing ability. A training signal generated by the external diagnostic device is detected by the interface circuit on initialization and used to derive sampling point timings.

A data processing apparatus controls cross-triggering of diagnostic processes on a plurality of processing devices. The data processing apparatus comprises a routing module having a plurality of broadcast channels, one or more of the broadcast channels being operable to indicate the occurrence of a diagnostic event on one or more of the plurality of processing devices. The data processing apparatus also comprises an mapping module associated with a corresponding processing device. The interface module programmably asserts diagnostic event signals from the associated processing device to one or more of the plurality of broadcast channels and programmably retrieves diagnostic events signals from processing devices other than the associated processing device from one or more of the plurality of broadcast channels. The retrieved diagnostic event data is used to facilitate triggering of a diagnostic process on the associated processing device in dependence upon said retrieved diagnostic event data.

Cross-triggering of processing devices

A data processing systemhas a base data address regionand a bit-band data address region. Memory accesses to the bit-band data address regionare converted into memory accesses to the base data address region. In the process of this conversion specific bits within the base data address regionare picked out for access whether that be via a read-modify-write operation or a masked read operation as appropriate. In this way, bit access is provided to data values within the base data address regionby addressing specific address locations within the bit-band data address region

Access to bit values within data words stored in a memory

A data processing system nested interrupt controllerresponsive to priority level valuesassociated with respective interrupt handling programs to control the execution of those interrupt handling programs. The priority level values have a first portionwhich controls whether or not a pending interrupt handling program will pre-empt an already active interrupt handling program and a second portionwhich controls which of a plurality of pending interrupt handling programs will be executed next when they share the same value for the first portion of their priority level value.

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Walnut Creek, CA, United States of America

Ian Field