Foundry Networks, Inc.

A 10 Networks, Incorporated

National Semiconductor Corporation

Ian Edward Davis

Aris Wong

Rajkumar Ramniranjan Jalan

Gurudeep Kamat

Ronak Patel

Joseph E Herbst

Jeffrey A Prince

Methods and systems for load balancing are disclosed. An example method for load balancing commences with receiving a data packet from a host device. The method further includes identifying a header field of the data packet. After identifying the header field of the data packet, the method proceeds with matching the data packet to a network service based on the header field. Thereafter, the method generates a header field block for the data packet based on the network service. The method further includes sending the data packet to a processor module. The data packet is processed based on the header field block.

Processing packet header with hardware assistance

Hardware-based packet editor receives a packet editing script which includes script entries indicating modifications to a data packet and a data block with data for the modified data packet. For a script entry in the packet editing script, the packet editor copies data in the data block at a block location and with a block length identified in the script entry into a packet buffer. The packet editor repeats the copying for the remaining script entries for the modified data packet. The packet editor then generates the modified data packet with the data in the packet buffer. The packet editing script is generated such that a script entry is created for data to be included in the modified data packet and data to be inserted into the modified data packet. Creation of a script entry is omitted for data to be removed.

Hardware-based packet editor

In processing data packet headers, a packet pre-processor is configured with at least one predetermined header field identifier. The packet pre-processor detects at least one header field identifier in a header field of a data packet received over a communication session between a host and a server, matches the predetermined header field identifier to the header field identifier in the data packet, generates a header report block comprising information corresponding to the header field identifier in the data packet, and sends the data packet and the header report block to a processor module for processing the data packet based on the header report block. The processor module receives the data packet and the header report block from the packet pre-processor, retrieves a service policy using the header report block, applies the service policy to the data packet, and sends the data packet to the host or the server.

In processing Hypertext Transfer Protocol (HTTP) headers, a packet pre-processor is configured with at least one predetermined header field identifier. The packet pre-processor detects at least one header field identifier in a header field of an HTTP packet received over an HTTP session between a host and a server, matches the predetermined header field identifier to the header field identifier in the HTTP packet, generates a header report block comprising information corresponding to the header field identifier in the HTTP packet, and sends the HTTP packet and the header report block to a processor module for processing the HTTP packet based on the header report block. The processor module receives the HTTP packet and the header report block from the packet pre-processor, retrieves a service policy using the header report block, applies the service policy to the HTTP packet, and sends the HTTP packet to the host or the server.

Method to process HTTP header with hardware assistance

A switching device comprising one or more processors coupled to a media access control (MAC) interface and a memory structure for switching packets rapidly between one or more source devices and one or more destination devices. Packets are pipelined through a series of first processing segments to perform a plurality of first sub-operations involving the initial processing of packets received from source devices to be buffered in the memory structure. Packets are pipelined through a series of second processing segments to perform a plurality of second sub-operations involved in retrieving packets from the memory structure and preparing packets for transmission. Packets are pipelined through a series of third processing segments to perform a plurality of third sub-operations involved in scheduling transmission of packets to the MAC interface for transmission to one or more destination devices.

Pipeline method and system for switching packets

According to an embodiment of the invention, a network device such as a router or switch provides efficient data packet handling capability. The network device includes one or more input ports for receiving data packets to be routed, as well as one or more output ports for transmitting data packets. The network device includes an integrated port controller integrated circuit for routing packets. The integrated circuit includes an interface circuit, a received packets circuit, a buffer manager circuit for receiving data packets from the received packets circuit and transmitting data packets in one or more buffers and reading data packets from the one or more buffers. The integrated circuit also includes a rate shaper counter for storing credit for a traffic class, so that the integrated circuit can support input and/or output rate shaping. The integrated circuit may be associated with an IRAM, a CAM, a parameter memory configured to hold routing and/or switching parameters, which may be implemented as a PRAM, and an aging RAM, which stores aging information. The aging information may be used by a CPU coupled to the integrated circuit via a system interface circuit to remove entries from the CAM and/or the PRAM when an age count exceeds an age limit threshold for the entries.

Method and apparatus for efficiently processing data packets in a computer network

Flexible method for processing data packets in a network routing system for enhanced efficiency and monitoring capability

The system of the present invention provides data transmission speeds at or in excess of 10 gigabits per second between one or more source devices and one or more destination devices. The system comprises a media access control (MAC) interface to facilitate receipt and transmission of packets over a physical interface. A first field programmable gate array is coupled to the MAC interface and operative to receive packets from the MAC interface and configured to perform initial processing of packets, which are dispatched to a first memory. A second field programmable gate array is operative to retrieve packets from the first memory and configured to compute an appropriate destination, which is used to dispatch packets to a backplane. A third field programmable gate array is provided that is operative to receive packets from the backplane and configured to organize the packets for transmission, which are dispatched to a second memory. A fourth field programmable gate array is coupled to the MAC interface and operative to retrieve packets from the second memory and configured to schedule the transmission of packets to the MAC interface for transmission to one or more destination devices.

Growing community of inventors

Fremont, CA, United States of America

Ian Edward Davis