Apple Inc.

Ian D Kountanis

Conrado Blasco

Muawya M Al-Otoom

Pruthivi Vuyyuru

Douglas C Holman

Ronald P Hall

Niket K Choudhary

Wei-Han Lien

Ethan R Schuchman

Ramesh B Gunna

David James Williamson

Kulin N Kothari

Conrado Blasco-Allue

Shyam Sundar

Haoyan Jia

Jeffry E Gonion

Yannick L Sierra

Gerard Richard Williams

Brett Stanley Feero

Richard F Russo

Shih-Chieh Wen

Michael Lance Karm

Deepankar Duggal

Steven Andrew Myers

Amit Kumar

Sean M Reynolds

Ilhyun Kim

André Seznec

James B Keller

Mary Douglass Brown

Nikhil Gupta

Rajat Goel

Mahesh K Reddy

Constantin Pistol

James R Hakewill

Abhishek Kumar

Siavash Zangeneh Kamali

A processor may include a conditional instruction prediction tracking circuit. During fetch of a conditional instruction from memory to an instruction cache of the processor, the conditional instruction prediction tracking circuit may predict whether the conditional instruction is biased. Responsive to a prediction that the conditional instruction is biased, the conditional instruction prediction tracking circuit may cause the conditional instruction to be executed according to the predicted bias. Sometimes the conditional prediction tracking circuit may cause the conditional instruction to be re-coded such that it may be executed as an unconditional instruction.

Biased conditional instruction prediction

An apparatus includes a sequential fetch circuit configured to provide a given sequential fetch address for use in a fetch request, and a sequential prediction circuit configured to store, for one or more sequential fetch addresses, respective sets of sequential fetch parameters for use in subsequent fetch requests. The apparatus further includes a fetch control circuit configured to, based at least on retrieving a particular sequential fetch address from the sequential fetch circuit, use the particular sequential fetch address to determine whether a particular set of sequential fetch parameters exists in the sequential prediction circuit. The fetch control circuit is also configured to, based at least on a determination that the particular set of sequential fetch parameters exists, use the particular set of sequential fetch parameters to create a next fetch request to retrieve instructions starting at the particular sequential fetch address.

Instruction fetch using a sequential prediction circuit

Systems, apparatuses, and methods for efficient handling of subroutine epilogues. When an indirect control transfer instruction corresponding to a procedure return for a subroutine is identified, the return address and a signature are retrieved from one or more of a return address stack and the memory stack. An authenticator generates a signature based on at least a portion of the retrieved return address. While the signature is being generated, instruction processing speculatively continues. No instructions are permitted to commit yet. The generated signature is later compared to a copy of the signature generated earlier during the corresponding procedure call. A mismatch causes an exception.

Systems and methods for optimizing authentication branch instructions

A system and method for efficiently protecting branch prediction information. In various embodiments, a computing system includes at least one processor with a branch predictor storing branch target addresses and security tags in a table. The security tag includes one or more components of machine context. When the branch predictor receives a portion of a first program counter of a first branch instruction, and hits on a first table entry during an access, the branch predictor reads out a first security tag. The branch predictor compares one or more components of machine context of the first security tag to one or more components of machine context of the first branch instruction. When there is at least one mismatch, the branch prediction information of the first table entry is not used. Additionally, there is no updating of any branch prediction training information of the first table entry.

Indirect branch predictor storing encrypted branch information fields

An apparatus includes an instruction cache circuit and an instruction fetch circuit. The instruction fetch circuit is configured to retrieve, from the instruction cache circuit, a fetch group that includes a plurality of instructions for execution by a processing circuit, and to make a determination that the fetch group includes a control transfer instruction that is predicted to be taken. A target address associated with the control transfer instruction is directed to an instruction within the fetch group. The instruction fetch circuit is further configured to, based on the determination, alter instructions within the fetch group in a manner that is based on a type of the control transfer instruction.

Using a next fetch predictor circuit with short branches and return fetch groups

Techniques are disclosed relating to predicting a next fetch address based on a current fetch address and history information. In some embodiments, tracking circuitry generates history information based on respective addresses corresponding to multiple control transfer instructions in a stream of executed instructions. Prediction circuitry may predict a next fetch address based on a current fetch address and the history information, including to: index into a first prediction table based on at least a portion of the current fetch address and at least a portion of the history information, compare tag data for an indexed location in the first prediction table with a tag that includes at least a portion of the current fetch address, and in response to a comparison hit in the first prediction table, provide a predicted next fetch address from the first prediction table.

Next fetch prediction using history

An apparatus includes a processor core that includes an instruction decode circuit and a control circuit. The instruction decode circuit is configured to decode instructions, including a plurality of store instructions used to store information in a memory hierarchy. The control circuit is configured, after a particular store instruction is decoded, to preserve store information related to the particular store instruction, including a first program counter value for the particular store instruction. In response to decoding a subsequent load instruction with a corresponding second program counter value, the control circuit is configured to determine, using the first and second program counter values, whether a dependency has been established between the subsequent load instruction and the particular store instruction. In response to a determination that the dependency has been established, the control circuit is configured to use the preserved store information to perform the subsequent load instruction.

Program counter zero-cycle loads

A multi-degree branch predictor is disclosed. A processing circuit includes an instruction fetch circuit configured to fetch branch instructions, and a branch prediction circuit having a plurality of prediction subcircuits. The prediction subcircuits are configured to store different amounts of branch history data with respect to other ones, and to receive an indication of a given branch instruction in a particular clock cycle. The prediction subcircuits implement a common branch prediction scheme to output, in different clock cycles, corresponding predictions for the given branch instruction using the different amounts of branch history data and cause, instruction fetches to be performed by the instruction fetch circuit. The prediction subcircuits are also configured to override, in subsequent clock cycles, instruction fetches caused by prediction subcircuits with comparatively less branch history data based on contrary predictions performed in subsequent clock cycles by prediction subcircuits with more branch history data.

Multi-degree branch predictor

A processor may include a bias prediction circuit and an instruction prediction circuit to provide respective predictions for a conditional instruction. The bias prediction circuit may provide a bias prediction whether a condition of the conditional instruction is biased true or biased false. The instruction prediction circuit may provide an instruction prediction whether the condition of the conditional instruction is true of false. Responsive to a bias prediction that the condition of the conditional instruction is biased true or biased false, the processor may use the bias prediction from the bias prediction circuit to speculatively process the conditional instruction. Otherwise, the processor may use the instruction prediction from the instruction prediction circuit to speculatively process the conditional instruction.

Conditional instructions prediction

An apparatus includes a processor circuit that includes a return address stack circuit, a return prediction circuit, and a fetch control circuit. The return prediction circuit is configured to store, for previously accessed return addresses, fetch parameters for next fetch addresses. The fetch control circuit is configured to in response to a fetch of a call instruction, push a return address onto the return address stack circuit. In response to a fetch of a return instruction that corresponds to the call instruction, the fetch control circuit is further configured to retrieve the return address from the return address stack circuit, and to create, using the return address and fetch parameters retrieved from the return prediction circuit, a next fetch request to retrieve instructions subsequent to the return instruction.

Instruction fetch using a return prediction circuit

A processor may include an instruction distribution circuit and a plurality of execution pipelines. The instruction distribution circuit may distribute a conditional instruction to a first execution pipeline for execution when the conditional instruction is associated with a prediction of a high confidence level, or to a second execution pipeline for execution when the conditional instruction is associated with a prediction of a low confidence level. The second execution pipeline, not the first execution pipeline, may directly instruct the processor to obtain an instruction from a target address for execution, when the conditional instruction is mispredicted. Thus, when the conditional instruction is distributed to the first execution pipeline for execution and determined to be mispredicted, the first execution pipeline may cause the conditional instruction to be re-executed in the second execution pipeline to cause the instruction from the correct target address to be obtained for execution.

Conditional instructions distribution and execution on pipelines having different latencies for mispredictions

Techniques are disclosed relating to signature-based instruction prefetching. In some embodiments, processor pipeline circuitry executes a computer program that includes control transfer instructions, such that the execution follows a taken path through the computer program. First signature prefetch table circuitry indicates prefetch addresses for signatures generated using a first signature generation technique and second signature prefetch table circuitry indicates prefetch addresses for signatures generated using a second, different signature generation technique. Signature prefetch circuitry, in response to a prefetch training event, determines a first signature according to the first technique and a second signature according to the second technique and selects one but not both of the first and second signature prefetch tables to train using the first signature or the second signature.

Multi-table signature prefetch

Indirect branch predictor storing encrypted branch information fields and security tag for security protection

In an embodiment, an indirect branch predictor generates indirect branch predictions based on one or more register values. The register values may be the contents of registers on which the indirect branch instruction is directly or indirectly dependent for generating the branch target address, for example. In an embodiment, at least one of the registers may be a source for a load instruction, and the indirect branch may be dependent (directly or indirectly) on the target of the load. In an embodiment, the indirect branch predictor may be one of at least two indirect branch predictors in a processor. The other indirect branch predictor may be based on a fetch address, or PC, associated with the indirect branch instruction. The other indirect branch predictor may generate a first predicted target address, and the indirect branch predictor may generate a second predicted target address for the same indirect branch instruction.

Indirect branch predictor based on register operands

Growing community of inventors

Santa Clara, CA, United States of America

Ian D Kountanis