Altera Corporation

Ian Chesal

Terry Borer

Stephen D Brown

Kevin Chan

David Wolk Mendel

Vaughn Betz

Gregg William Baeckler

Deshanand Pratap Singh

Valavan Manohararajah

James G Schleicher

Babette Van Antwerpen

Richard Yuan

Gabriel Quan

Mike Hutton

Boris Ratchev

Yaska Sankar

Ivan Hamer

Paul McHardy

Chris Sanford

Karl Schabas

Minh V Mac

Subianto Windoro

Irene Sujanto

Sheac Yee Lim

The time and computational resources needed to evaluate the potential input parameter settings in a design space is decreased by determining probabilities of improvement for input parameter settings in the design space and eliminating input parameter values that have low probabilities of improvement from the design space prior to compilation. The probability of improvement for input parameter settings is an estimate of the likelihood that the compilation of the user design using the set of input parameter settings will improve the performance of the user design with respect to one or more design goals, such as timing, power, or resource usage. The probability of improvement for input parameter settings can be determined from an analysis of the compilation results of sample designs, from attributes and/or constraints of the user design, and/or from a correlation between the results of optimization algorithms applied to the user design.

Directed design space exploration

A method for designing a system on a target device utilizing field programmable gate arrays (FPGAs) includes identifying a group of components associated with a critical signal in the system. A first copy and a second copy of the group of components are generated where the first copy is driven by a first signal at a first state and the second copy is driven by a second signal at a second state. The system is configured to select an output of one of the first copy and the second copy in response to the critical signal.

Method and apparatus for performing layout-driven optimizations on field programmable gate arrays

Techniques for optimizing the placement and synthesis of a circuit design on a programmable integrated circuit are provided. The performance of a circuit design is analyzed after it has been compiled with different values for selected input parameters. The input parameter values that produce the best results for an output metric are then chosen to synthesis and place the circuit design on the programmable integrated circuit. In one embodiment, the values of the output metrics are averaged for all test compiles that share the same input parameters, but different seeds. In another embodiment, the compile with the best output metrics, as determined by the user, are selected. These techniques allow a user to automatically trade off compile-time to get a better-optimized circuit.

Techniques for automated sweeping of parameters in computer-aided design to achieve optimum performance and resource usage

Techniques are provided for converting a circuit design file so that it is compatible with a new programmable IC. Black box declarations and instances of black boxes in the circuit design file are located automatically. Then, information about the function and structure of the black boxes is gathered from various user files. This information is used to convert the black box declarations and instances into equivalent declarations and instances that are compatible with the new programmable IC. The design conversion process is performed quickly and automatically with minimal user input. User input is only needed to identify recognized black boxes.

Techniques for editing circuit design files to be compatible with a new programmable IC

A method for designing a system on a target device utilizing field programmable gate arrays (FPGAs) includes identifying registers on near-critical paths. The registers are moved to shorten lengths of one or more near-critical paths.

Method and apparatus for performing retiming on field programmable gate arrays

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Toronto, Canada

Ian Chesal