Hewlett-packard Company

Hewlett-packard Development Company, L.p.

Ian A Elliott

Jeffrey Joel Walls

John Marks

Bryan G Prouty

John R Diamant

Anthony C Barkans

Alan D Ward

Lawrence G Mahoney

James M Stearns

David R Lechtenberg

A computer system and method responds to a compromise of a first computer node by automatically hardening one or more uncompromised nodes of the system.

Automatic hardening of an uncompromised computer node

One method embodiment includes defining a first package to be opened by a computing device. The method includes associating installation content to be installed on the computing device with the first package. The first package includes a second package that includes the installation content to be installed and the first package includes package functionality information to determine whether a particular package functionality can be utilized by the computing device.

Package compatibility

A system and method for a computer system to recognize and initialize an arrangement of a plurality of physical monitors as a single logical screen (SLS). The invention translates a user's window operation request directed to the SLS into an SLS function. The SLS function is then translated into a plurality of device dependent functions, each of which performs the user's requested window operation on one physical monitor. The translation of the SLS function comprises an unwrapping of the SLS function by removing the SLS function and installing the plurality of device dependent functions, and the wrapping of the plurality of device dependent functions by removing the plurality of device dependent functions and installing the SLS function. The invention implements each of the unwrapping and wrapping operations in two assignment instructions. The invention further comprises the capability of generating a single simultaneous display wherein the image on one physical monitor is displayed on each physical monitor of the SLS configuration.

Design and method for a large, virtual workspace

An interactive, information logging and processing tool that provides information regarding a process's data structure utilization to reduce the working set of a process's dynamically allocated memory. The actual working set (AWS) determinant determines which portions of the dynamically-allocated pages, referred to as the process's virtual memory (VM) working set (VWS) are actually used. It then determines the actual working set of a dynamically allocated memory for a given benchmark. The basic approach of the AWS determinator is to observe which data structures cause page faults when the targeted process is severely thrashing. AWS determinator includes a data logger and a data analyzer. The data logger ensures that a consistent benchmark is achieved in order to obtain the most accurate results, increases the number and granularity of heap page faults for the target process to enable the page fault mechanism of the processor to count the number of times the associated data structure is accessed, and log all heap page faults and transactions. The data analyzer is an interactive, information processing tool that efficiently process the large amounts of data logged by the data logger during a benchmark run. The data analyzer also allows users to interactively explore the processed data, to gain insights into a process's heap AWS. The data analyzer correlates each block of heap memory to a particular C data structure. Then, after the benchmark is completed and the above information is logged and correlated, an information processing step is performed wherein an approximate determination of the targeted process's heap AWS is performed.

System and method for determining a process's actual working set and

First next and second next pixel locations are selected simultaneously from among adjacent pixel locations and represent a straight line segment defined by two end locations and having a slope of one or less. An initialization process uses the .DELTA.X and .DELTA.Y of the desired line segment to find various constants, including an initial error term, an error term increment, an error term decrement, an error term double increment, an error term double decrement, and an error term increment-then-decrement. These represent, respectively, an increment in the X location without an increment to the Y location (a step S), an increment in the X location and an increment in the Y location (a jump J), a step followed by a step (two steps SS), two jumps (JJ), and either of a step-then-jump or a jump-then-step (SJ/JS). These five operations correspond to the only possible locations that might be selected, given any starting location. Of the five operations, exactly one of the first two will be for the first next location, while exactly one of the last three will be for the second next location. The present error term is an input to three different adders. Another input to each of the adders is one of the constants for S or J and two of the constants for SS, JJ and SJ/JS. The three additions proceed simultaneously. The initial error term and the resulting three trial error terms can be inspected in relation to error term limits. When the Bresenham Algorithm is implemented, these comparisons are simple determinations of sign. A logic circuit responsive to the error term inspection indicates which combination of the operations S and J correspond to the desired path. A corresponding frame buffer operation code is sent to the a frame buffer address controller. Once the selection is made the error term value for the selected second next pixel location is captured and made to be the error term input for the adders, and the process is ready to select another two pixel locations. If .DELTA.X is an odd number then the second next position is not needed for the final sequence of frame buffer operation codes, and it to be suppressed.

Growing community of inventors

Fort Collins, CO, United States of America

Ian A Elliott