Lsi Logic Corporation

Fmax Technologies, Inc.

Tyco Electronics Corporation

Cosemi Technologies, Inc.

Iain Ross Mactaggart

Alan S Fiedler

David Erich Tetzlaff

James R Welch

Jonathan Alois Schmitt

Roger L Roisen

John J Stronczer

Robert Monroe Smith

Charles Phillip McClay

Wu-Chun Chou

Apparatus and methods are provide for a multichannel clock and data recovery (CDR) device that shares information between channels. In an example, a multiple channel communication circuit can include a plurality of clock and data recovery (CDR) circuits, each CDR circuit of the plurality of CDR circuits associated with a channel of the multiple channel communication circuit. In certain examples, each CDR circuit can be configured to detect an incoming stream of data from the channel, to determine a setting of one or more parameters for correctly sampling the data from the incoming stream, and to share an indication of the setting of the one or more parameters to an adjacent CDR circuit of the plurality of CDR circuits.

Multichannel CDR with sharing of adaptation hints and learning

Apparatus and methods are provide for frame synchronization and clock and data recovery. In an example, a method can include receiving initial data of a stream of information, sampling the stream of information a plurality of times per unit interval to provide a plurality of sample intervals, integrating transition information for each sample interval, and selecting a sampling phase to sample each symbol of the stream of data using the integrated transition information.

Apparatus and methods for burst mode clock and data recovery for high speed serial communication links

A power efficient device for driving a load comprising a low current path and a high current path, wherein the high current path is driven by a first voltage source. In order to accommodate larger turn on voltages of possible load devices while maintaining low power operation, an additional voltage source exceeding the voltage source in the high current path is introduced in the low current path.

Pass device with boost voltage regulation and current gain for VCSEL driving applications

An eye quality monitoring system may include an eye quality monitor that includes a charge pump that is configured to output (a) a first charge in a first direction upon detection of a first transition of a sampled non-return-to-zero (NRZ) data signal in a first region of a unit interval of an eye pattern, and (b) a second charge in a second direction upon detection of a second transition of the sampled NRZ data signal in a second region of the unit interval of the eye pattern. The first direction is opposite from the second direction. The eye quality monitor is configured to form an eye quality output that relates to a quality of the eye pattern based on the first and second charges.

Eye quality monitoring system and method

A data lock detection system may include a receiver configured to receive a data signal, a phase detector configured to output a phase detection output signal representative of the data signal with respect to a clock signal, and a lock detector configured to receive the phase detection output signal. The lock detector is configured to determine a presence of a frequency difference between the data signal and the clock signal and output a lock determination output signal that indicates if the data signal is locked or unlocked with the clock signal.

Non-return-to-zero (NRZ) data lock detection system and method

Embodiments of a device and circuit implementing a digitally controlled oscillator with reduced analog components. In an example, the digitally controlled oscillator can include a phase accumulator controlled by a stall circuit to selective stall the phase accumulator. In some examples, the digitally controlled oscillator can include a phase select circuit to select multiple phases of a phase select circuit based on the output of the phase accumulator. In some examples, these selected phases can then be used by a phase interpolator to generate a synthetic clock signal.

Dynamic clock phase control architecture for frequency synthesis

A driver device for a laser includes a control device configured to generate a control current, an NPN differential amplifier connected to the control device and configured to superimpose a modulation current onto the control current to generate a combined current, and a laser activation switch coupled to the output of the NPN differential amplifier, the laser activation switch operating the laser utilizing the combined current. Also described herein is a communication system including a driver device.

Driver for supplying modulated current to a laser

Digitally controlled oscillator

An integrated circuit I/O buffer has an output driver. The output driver includes first, second and third voltage supply terminals and a pad terminal. A pad pull-up transistor is coupled in series between the first voltage supply terminal and the pad terminal and has a pull-up control terminal. A pad pull-down transistor is coupled in series between the second voltage supply terminal and the pad terminal and has a pull-down control terminal. A voltage protection transistor is coupled between the pad terminal and the pad pull-down transistor. The voltage protection transistor has a control terminal and a capacitance between the control terminal and the pad terminal. A resistor is coupled in series between the control terminal of the voltage protection transistor and the third voltage supply terminal and forms a resistor-capacitor (RC) circuit with the capacitance.

Integrated circuit I/O buffer having pass gate protection with RC delay

A high speed capture latch includes differential data inputs, a latch clock input, a boost clock input, a current steering circuit, a switched current source, a latch element and first and second boost current sources. The current steering circuit has first and second differential control terminals which are coupled to the differential data inputs and control current through first and second current paths, respectively. The switched current source is coupled between the current steering circuit and a first voltage supply terminal and has a control terminal coupled to the latch clock input. The latch element is coupled between a second voltage supply terminal and the current steering circuit and provides a latch output. The first boost current source is coupled to the first current path between the latch element and the current steering circuit and has a control terminal coupled to the boost clock input. The second boost current source is coupled to the second current path between the latch element and the current steering circuit and has a control terminal coupled to the boost clock input.

High speed capture latch

A voltage-controlled oscillator includes at least one voltage-controlled delay element and a reference voltage generator. The voltage-controlled delay element has first and second voltage supply inputs, a control voltage input, a signal input and a signal output. The reference voltage generator has a voltage input coupled to the control voltage input and a voltage output coupled to the first voltage supply input.

VCO supply voltage regulator

A self-timed phase detector for detecting the phase of an input signal, such as a high speed serial data stream. The self-timed phase detector includes a precharged latch, a phase detector circuit and a data valid gate. The precharged latch has a latch input, a sample clock input and first and second complementary latch outputs. The first and second complementary latch outputs have an active state and a precharged state. The phase detector circuit is coupled to the first latch output and generates a phase signal on a phase output as a function of the phase of the input signal. The data valid gate is coupled to the phase output for passing the phase signal when the latch outputs are in the active state and for blocking the phase signal when the latch outputs are in the precharged state.

Growing community of inventors

Eden Prairie, MN, United States of America

Iain Ross Mactaggart