Northern Telecom Limited

Group IV Semiconductor, Inc.

Mcmaster University

Iain D Calder

George Chik

Thomas W Macelwee

Thomas Macelwee

Hussein M Naguib

Abdalla A Naem

Vu Q Ho

E Steven Hill

Ismail T Emesh

Gurvinder Jolly

Lynnette D Madsen

Nur M Serinken

Carla Miner

Albert R Boothroyd

Steven E Hill

James Gale

Peter Mascher

James J White

Jacek Wojcik

Norman C Fletcher

An engineered structure of a light emitting device comprises multiple layers of alternating active and buffer materials disposed between AC or DC electrodes, which generate an electric field. The active layers comprise luminescent centers, e.g. group IV semiconductor nanocrystals, in a host matrix, e.g. a wide bandgap semiconductor or dielectric material such as silicon dioxide or silicon nitride. The buffer layers are comprised of a wide bandgap semiconductor or dielectric material, and designed with a thickness, in the direction of an applied electric field, that ensures that electrons passing therethrough picks up enough energy to excite the luminescent centers in the adjacent active layer at an excitation energy to emit light efficiently at a desired wavelength.

Engineered structure for solid-state light emitters

Electroluminescent (EL) light emitting structures comprises one or more active layers comprising rare earth luminescent centers in a host matrix for emitting light of a particular color or wavelength and electrodes for application of an electric field and current injection for excitation of light emission. The host matrix is preferably a dielectric containing the rare earth luminescent centers, e.g. rare earth doped silicon dioxide, silicon nitride, silicon oxynitrides, alumina, dielectrics of the general formula SiAlON, or rare earth oxides. For efficient impact excitation, corresponding drift layers adjacent each active layer have a thickness related to a respective excitation energy of an adjacent active layer. A stack of active layers emitting different colors may be combined to provide white light. For rare earth species having a host dependent emission spectrum, spectral emission of the stack may be tuned by appropriate selection of a different host matrix in successive active layers.

Engineered structure for high brightness solid-state light emitters

A light emitting device includes an active layer structure, which has one or more active layers with luminescent centers, e.g. a wide bandgap material with semiconductor nano-particles, deposited on a substrate. For the practical extraction of light from the active layer structure, a transparent electrode is disposed over the active layer structure and a base electrode is placed under the substrate. Transition layers, having a higher conductivity than a top layer of the active layer structure, are formed at contact regions between the upper transparent electrode and the active layer structure, and between the active layer structure and the substrate. Accordingly the high field regions associated with the active layer structure are moved back and away from contact regions, thereby reducing the electric field necessary to generate a desired current to flow between the transparent electrode, the active layer structure and the substrate, and reducing associated deleterious effects of larger electric fields.

Pixel structure for a solid state light emitting device

A solid state light emitting device comprises one or more active layers comprising semiconductor nano-particles in a host matrix, e.g. silicon nano-particles in silicon dioxide or silicon nitride. The incorporation of carbon in the active layers provides a great improvement in performance through shortened decay time and enhance emission spectra, as well as reliability and lifetime. The emission wavelengths from the nano-particles can be made to correspond to the quantization energy of the semiconductor nano-particles, which allows the entire visible range of the spectrum be covered. Ideally an engineered structure of alternating active and buffer material layers are disposed between AC or DC electrodes, which generate an electric field. The buffer layers are comprised of a wide bandgap semiconductor or dielectric material, and are designed with a thickness, in the direction of an applied electric field, that ensures that electrons passing therethrough picks up enough energy to excite the nano-particles in the adjacent active layer at a sufficient excitation energy to emit light efficiently at a desired wavelength.

Carbon passivation in solid-state light emitters

A capacitor structure for a memory element of an integrated circuit is provided. The capacitor is formed within a via hole defined through a first dielectric layer, and comprises a bottom electrode defined by an underlying conductive layer, and a capacitor dielectric filling the via with a dielectric barrier layer lining the via and separating the capacitor dielectric from the first dielectric layer. The capacitor dielectric is characterized by a material with high dielectric strength, preferably a ferroelectric material. An overlying conductive layer defines a top electrode contacting the capacitor dielectric. The barrier layer may comprise dielectric sidewall spacer formed within the via, or alternatively may comprise a region of mixed composition formed by interdiffusion of the first dielectric layer and the capacitor dielectric. The resulting capacitor structure is simple and compact, and may be fabricated with known CMOS, Bipolar or Bipolar-CMOS processes for submicron VLSI and ULSI integrated circuit.

Structure and method of making a capacitor for an intergrated circuit

A method is provided for forming a capacitor structure for a memory element of an integrated circuit. The method comprises providing a first conductive electrode, forming a layer of a first dielectric material thereon, opening a via hole through the dielectric layer, providing within the via opening a capacitor dielectric having a higher dielectric strength than the first dielectric, the capacitor dielectric contacting the first electrode, planarizing the resulting structure and then forming a second conductive electrode thereon. Preferably, when the second dielectric comprises a ferroelectric dielectric material, sidewalls of the via opening are lined with a dielectric barrier layer to provide diffusion barrier between the ferroelectric and first dielectric layer. Advantageously, planarization is accomplished by chemical mechanical polishing to provide fully planar topography. The method provides a capacitor of a simple, compact structure which may be integrated with CMOS, Bipolar and Bipolar CMOS processes for submicron VLSI and ULSI integrated circuits.

Method of making a capacitor for an integrated circuit

A silicon-on-insulator substrate having a very low threading dislocation density is made by implanting oxygen ions into a silicon substrate while heating the substrate to form a layer of silicon dioxide buried in the silicon substrate and annealing the implanted substrate at high temperature in a novel furnace incorporating a polysilicon tube to constrain the annealing temperature to be uniform over the entire substrate. The silicon-on-insulator substrate is particularly useful for the manufacture of semiconductor devices formed in thin silicon films.

Silicon-on-insulator substrates annealed in polysilicon tube

In a metal oxide semiconductor field effect transistor fabrication process, refractory metal is deposited over designated source and drain areas within a silicon substrate. Refractory metal and silicon at the interface is then mixed by ion implantation of a heavy neutral ion species such as germanium. To minimize source/drain junction depth, the source and drain locations can be subjected to bombardment by a lighter ion such as silicon which amorphizes silicon to a predetermined depth under the designated source and drain regions and so substantially confines dopant diffusion to the silicon amorphized region. To render the source and drain of desired conductivity type, an ion implantation of a non-neutral ion is then performed.

Process of fabricating MOS devices having shallow source and drain

A vertically integrated CMOS logic gate has spaced semiconductor layers with control gates located between the layers and insulated from them by gate oxide. Transistors formed in one semiconductor layer are vertically aligned with transistors formed in the other semiconductor layer. Pairs of vertically coincident transistors have common control gates and certain of the pairs have integral drain regions. Transistors in one layer are series connected in an open loop configuration and transistors in the other layer are parallel connected in a closed loop configuration. The logic gate function depends on voltages applied to the common control gates and to the open and closed loops. By the vertical integration, a two-input NAND or NOR gate can be made using less area than that required for two simple MOS transistors.

Structure and fabrication of vertically integrated CMOS logic gates

In a process for manufacturing vertically integrated MOS devices and circuits, gate oxide and a gate are formed on a semiconductor substrate such as a silicon substrate. A layer of polysilicon is then deposited over the wafer, the polysilicon contacting the substrate silicon through a window in the gate oxide. The substrate silicon and the polysilicon are then laser melted and cooled under conditions that encourage crystal seeding from the substrate into the polysilicon over the gate. Subsequently, ions are implanted into the silicon substrate and the polysilicon to form source and drain regions. By introducing the source and drain dopants after melt associated seeding of the polysilicon, the risk of dopant diffusion into the device channel regions is avoided.

Fabrication of stacked MOS devices utilizing lateral seeding and a

An integrated circuit is fabricated with some redundant capacity by forming potential electrically conducting links which can subsequently be made electrically when extra circuit capacity is required. Field oxide is grown on a silicon substrate and then a layer of polysilicon deposited over the oxide. At the redundancy sites where electrical connections may subsequently be made, an anti-reflective silicon nitride coating is deposited and photodefined. The areas of this coating are used as masks in order to diffuse dopant into the polysilicon at parts of the polysilicon laterally adjacent the redundancy sites. When later it is necessary to bring spare capacity into the circuit the complete circuit is scanned with a continuous wave laser. The laser melts the polysilicon under the nitride mask permitting the dopant to diffuse from the adjacent parts of the polysilicon and so form a conducting link. However under parts of the polysilicon not covered by an anti-reflective coating the polysilicon is not melted by the laser beam and so its conductivity remains unchanged. The fabrication process is self-aligned since the intrinsic or undoped region of the polysilicon is the same as the region which is melted. The method for making the electrical links does not require precise positioning and focussing of the laser beam as in known methods.

Laser activated polysilicon connections for redundancy

At each of a pair of linked terminals, an image is generated at local and remote input devices. The generated image is projected onto a viewing screen and, while exhibited, further locally or remotely generated data is used to alter the generated image and, consequently, to alter the projected image. Data can, for example, be generated by means of a document scanner and a manually operated X-Y pen digitizer.

Interactive viewgraph system

In a stacked metal-oxide-semiconductor (SMOS) transistor, the transistor source, drain and channel each have a lower part formed in a silicon substrate and an upper part composed of recrystallized polysilicon. The device gate is located between the upper and lower channel parts. By vertically integrating a MOS transistor, performance limitations imposed by the direct scaling approach to device miniaturization are avoided.

Stacked MOS transistor

In the manufacture of VLSI (very large scale integrated) MOS (metal-oxide-semiconductor) circuits, a polysilicon gate is deposited on an oxide layer overlaying a silicon substrate. Ideally, the polysilicon gate is made extremely small and with sharply defined vertical boundaries. The invention proposes depositing a polysilicon layer, covering a region of the layer with an antireflective coating, and laser annealing the layer. Laser radiation is absorbed to a higher level by the coated region than elsewhere and consequently the polysilicon layer in this region melts and recrystallizes into large grains. The polysilicon layer is then etched using etch conditions ensuring preferential etching of unrecrystallized polysilicon in comparison with recrystallized polysilicon. Consequently, except at the coated region, the polysilicon is etched quickly and there is very little undercutting of the gate region. Preferential etching methods based on differing dopant levels in polysilicon are known but do not produce the sharp edge definition enabled using the present process.

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Nepean, Canada

Iain D Calder