Texas Instruments Corporation

Ultrasoc Technologies Limited

Siemens Industry Software Gmbh

Mentor Graphics Corporation

Oracle America, Inc.

Iain Craig Robertson

Richard D Simpson

Keith Balmer

Andrew Brian Thomas Hopkins

David A Comisky

Michael D Asal

Sanjive Agarwala

Jeffrey L Nye

James G Littleton

Graham B Short

Karl M Guttag

John D Keay

Callum Stewart

Andre Szczepanek

Gajinder Singh Panesar

Michael Jonathan Thyer

Robert J Gove

Denis R Beaudoin

Nicholas K Ing-Simmons

Charles Lance Fuoco

Amarjit Singh Bhandal

Melvin Cheah

Hanan Moller

David J Hoyle

Michael Stephen Harwood

Richard G Williams

Christopher L Mobley

Gary L Swoboda

Christopher Jensen Read

Andrew Keith Joy

Eric Robert Hansen

Frank C Chiu

Richard Ward

Robert Simpson

Nicholas Ing Simmons

Ian Jones

Anup Pradhan

Jonathan Jeacocke

Rupert Baines

A processor supervisory unit for monitoring the program flow executed by a processor, the supervisory unit being arranged to store a set of values representing locations to which the program flow is expected to return after jumps in the program flow, the unit being capable of: in a first mode, on detecting a jump in the program flow to store a location value representing a location to which the program flow is expected to return from that jump; and in a second mode, on detecting a jump in the program flow to increment a counter associated with a location value representing a location to which the program flow is expected to return from that jump.

Handling trace data for jumps in program flow

An integrated circuit (IC) chip includes system circuitry having system memory, and a master processor and a checker processor configured to operate in lockstep; and monitoring circuitry comprising an internal lockstep monitor, a master tracer and a checker tracer. The internal lockstep monitor is configured to: observe states of internal signals of the master processor and the checker processor, compare corresponding observed states of the master processor and the checker processor, and if the corresponding observed states differ: trigger the master tracer to output stored master trace data recorded from the output of the master processor, and trigger the checker tracer to output stored checker trace data recorded from the output of the checker processor.

Monitoring processors operating in lockstep

A method of tracing instruction execution on a processor of an integrated circuit chip in real time whilst the processor continues to execute instructions during clock cycles of the processor. The instruction execution of the processor is monitored by counting the number of successive instructions which are retired contiguously in time to form an instruction count, and counting the number of subsequent contiguous clock cycles of the processor during which no instruction is retired to form a stall count. A trace message is generated which includes the instruction count and the stall count, and the trace message is outputted.

Generation of trace messages including an instruction retirement count and a stall count

A supervisory unit configured to supervise interconnect messages passing to or from an interconnect is provided. The supervisory unit is configured to, on receiving an interconnect message: store the interconnect message in a data store; compare the interconnect message to predetermined filter criteria; and select, in dependence on that comparison, one or more actions to be taken with respect to the interconnect message. The one or more actions are selected from the group including: permitting the interconnect message to pass unaltered; blocking the interconnect message from passing and permitting the interconnect message to pass in an altered state; and performing the one or more selected actions with respect to the interconnect message.

Message monitoring

A method of broadcasting event messages in a system-on-chip having system circuitry and monitoring circuitry for monitoring the system circuitry, the monitoring circuitry comprising units connected in a tree-based structure for routing communications through the system-on-chip, the tree-based structure comprising branches extending from a root unit, each branch comprising a plurality of units, each unit connected to a single unit above in the branch and a single unit below in the branch, whereby each unit routes communications to and from individually addressable entities above that unit in its branch, the tree-based structure further comprising crosslinks connecting corresponding units of adjacent branches, the method comprising: if an event is generated at an event unit or its local subsystem, routing an event message directly from that event unit to: any adjacent unit above the event unit in the event unit's branch, any adjacent unit below the event unit in the event unit's branch, and any corresponding unit of an adjacent branch to which the event unit is connected via a crosslink.

Broadcasting event messages in a System on Chip using a crosslinked tree structure

An integrated circuit chip has a set of communication units, each unit being configured to operate according to a protocol in which a data packet sent by one unit is receivable by one unit only, each unit being configured to send at least one packet having one of a plurality of tiers to at least one other unit and being configured to specify, for each tier, a subset of destination units to which packets of that tier are to be sent, wherein each unit is configured to: receive a packet having one of the plurality of tiers; determine the tier of the received packet; and sequentially send packets having a different tier to the tier of the received packet to each of the respective subset of destination units for the different tier.

Emulating broadcast in a network on chip

A communication device configured to communicate according to a data protocol in which data is carried in packets over a serial data link and the communication device is arranged: to form packets for transmission over the link in such a way that every packet commences with a first bit value; and between transmitting successive packets to continuously transmit a second bit value opposite to the first bit value over the link.

Packet data protocol

A communication unit and discoverable unit communicate according to a protocol in which unit addresses are not of a predetermined length. The communication unit sends a discovery request to the discoverable unit. The discoverable unit receives the discovery request and generates a discovery response. The discovery response comprises an address field of length unknown to the communication unit, populated with an address of the discoverable unit. The discovery response also comprises a flag following the address field. The discoverable unit sends the discovery response to the communication unit. The communication unit receives the discovery response and determines the address field length by counting the number of bits prior to the flag.

Variable address length communication protocol

A method of tracing transactions on an integrated circuit chip. The method comprises, for each transaction: extracting the transaction from interconnect circuitry of the integrated circuit chip, the transaction comprising an address signal and a data signal; applying a filtering condition to the address signal; only if the address signal does not fail the filtering condition, storing the address signal in an address trace buffer; storing the data signal in a data trace buffer; applying a triggering condition to the stored transaction; and outputting the stored transaction if the stored transaction matches the triggering condition.

Tracing interconnect circuitry

An integrated circuit, having a security supervision system, comprising a plurality of functional circuit blocks interconnected to collectively performing data processing tasks, one or more communication adaptors, having: (i) a hardware interconnection to the functional circuit blocks, whereby the communication adaptor senses the state and/or activity of the functional circuit block; (ii) memory storing definitions of state and/or activity of functional circuit block and actions for each definition; and (iii) processing circuitry comparing the state and/or activity of the functional block with each definition, such that when state and/or activity of the functional block corresponding to a stored definition is detected, perform the corresponding action. The memory stores a definition of state and/or activity characteristic of insecure operation of the functional circuit block and a corresponding action to partially disabling the functional circuit block and/or (ii) causing a message to be transmitted to a destination off the integrated circuit.

Integrated circuit security

A method of profiling transactions on an integrated circuit chip. The method comprises, for each transaction: extracting the transaction from interconnect circuitry of the integrated circuit chip; and filtering the transaction at a filtering circuit to determine which passband a parameter of the transaction lies within; sending an increment signal to a counter of a bank of counters, the counter having a counter value indicative of a number of transactions having the parameter lying within the passband; and outputting the counter values of the bank of counters.

Profiling transactions on an integrated circuit chip

A method of functionality testing system circuitry on an integrated circuit chip, the system circuitry comprising a plurality of sub-circuits and the integrated circuit chip further comprising debugging circuitry, the debugging circuitry comprising variability circuitry. The method comprises: at the system circuitry, performing a function by the sub-circuits performing concurrent actions; at the variability circuitry, altering relative timing of the concurrent actions so as to increase the likelihood of one or more errors in the system circuitry's performance of the function; and at the debugging circuitry, recording one or more errors in the system circuitry's performance of the function.

Functional testing of an integrated circuit chip

An integrated circuit chip device comprising: system circuitry; debugging circuitry configured to debug the system circuitry, the debugging circuitry being segmented into zones; wherein the debugging circuitry comprises an interconnect fabric configured to route debug messages through a zone from a zone entry node of the interconnect fabric to a zone exit node of the interconnect fabric; and wherein the debugging circuitry is configured to, on receiving a debug message at a zone entry node that is shorter than a specified length, modify the debug message to form a modified debug message by increasing the length of the debug message to the specified length.

Routing debug messages

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Cople, United Kingdom

Iain Craig Robertson