Lsi Corporation

Iain Clark

Juergen Dirks

A scan clock generator includes a clock signal input for receiving a clock signal, a scan shift mode signal input for receiving a scan shift mode signal, and a sequence controller coupled to the clock signal input for gating a selected number of clock signal pulses at a time to generate a sequence of nonconcurrent scan clock signals at separate outputs respectively in response to a first state of the scan shift mode signal.

On-chip scan clock generator for ASIC testing

A scan chain partition includes a serial input coupled to a scan input signal pin of a module under test. A plurality of scan sub-chains is coupled to the serial input. A scan sub-chain output multiplexer is coupled to the plurality of scan sub-chains for sequentially selecting only one of the scan sub-chains in response to a scan sub-chain control signal. A scan sub-chain controller generates the scan sub-chain control signal and gates a scan clock signal to only a scan clock input of the selected scan sub-chain.

Scan chain partition for reducing power in shift mode

A circuit for parametric testing of an integrated circuit includes an integrated circuit having a plurality of input buffers and a plurality of XOR gates. The plurality of XOR gates have a first input that is connected to an output of one of the input buffers and having a second input that is connected to an output of a preceding XOR gate to form an XOR logic tree.

Growing community of inventors

San Jose, CA, United States of America

Iain Clark