Taiwan Semiconductor Manufacturing Comp. Ltd.

I-Wen Wu

Mei-Yun Wang

Fu-Kai Yang

Chen-Ming Lee

Po-Yu Huang

Hsien-Cheng Wang

Shih-Wen Liu

Jia-Heng Wang

Chao-Hsun Wang

Peng Wang

Yun Lee

Kai-Hsuan Lee

Jr-Hung Li

Shih-Che Lin

Chun-Han Chen

Shih-Chieh Wu

Chang-Yun Chang

Ching-Feng Fu

Wei-Yuan Lu

Bo-Cyuan Lu

Guan-Ren Wang

Chun-An Lin

Shao-Ming Koh

Chi On Chui

Ping-Wei Wang

Shih-Hao Lin

Chung-Ting Ko

Jui-Lin Chen

Hsin-Ying Lin

Chao-Yuan Chang

Hsiao-Chiu Hsu

Ting Fang

Yen-Ming Chen

Feng-Cheng Yang

Jian-Hao Chen

Chia-Hsien Yao

A method includes forming a fin protruding from a substrate, forming a gate structure across the fin, forming an epitaxial feature over the fin, depositing a dielectric layer covering the epitaxial feature and over sidewalls of the gate structure, performing an etching process to form a trench, the trench dividing the gate structure into first and second gate segments and extending into a region of the dielectric layer, forming a dielectric feature in the trench, recessing a portion of the dielectric feature located in the region, selectively etching the dielectric layer to expose the epitaxial feature, and depositing a conductive feature in physical contact with the epitaxial feature and directly above the portion of the dielectric feature.

Metal gate structure cutting process

Methods and devices including an air gap adjacent a contact element extending to a source/drain feature of a device are described. Some embodiments of the method include depositing a dummy layer, which is subsequently removed to form the air gap. The dummy layer and subsequent air gap may be formed after a SAC dielectric layer such as silicon nitride is formed over an adjacent metal gate structure.

Semiconductor device contact structures and methods of fabricating thereof

A semiconductor structure includes a substrate, nanostructures over the substrate, and a gate structure wrapping around the nanostructures. The gate structure includes a gate dielectric layer and a gate electrode wrapping around the gate dielectric layer. The semiconductor structure further includes a source/drain feature in contact with the nanostructures, a contact etch stop layer over the source/drain feature, and a seal layer over the air spacer and the gate structure, and on a sidewall of the contact etch stop layer. The contact etch stop layer is separated from the gate structure by an air spacer.

Semiconductor structure and method for manufacturing the same

A semiconductor structure includes a channel member, a gate structure disposed over the channel member, a source/drain feature connected to the channel member and adjacent to the gate structure, a source/drain contact disposed below and connected to the source/drain feature, a backside dielectric feature disposed below the channel member, and a first dielectric layer and a second dielectric layer disposed between the backside dielectric feature and the source/drain contact. The first dielectric layer includes a low-k dielectric material.

Semiconductor transistor device having backside source/drain contact with a low-k spacer and method of forming the same

Semiconductor structures and methods are provided. An exemplary method according to the present disclosure includes receiving a fin-shaped structure comprising a first channel region and a second channel region, a first and a second dummy gate structures disposed over the first and the second channel regions, respectively. The method also includes removing a portion of the first dummy gate structure, a portion of the first channel region and a portion of the substrate under the first dummy gate structure to form a trench, forming a hybrid dielectric feature in the trench, removing a portion of the hybrid dielectric feature to form an air gap, sealing the air gap, and replacing the second dummy gate structure with a gate stack after sealing the air gap.

Isolation structures

Semiconductor structures and methods are provided. An exemplary method according to the present disclosure includes providing a workpiece including a semiconductor fin protruding from a substrate, a first placeholder gate and a second placeholder gate over channel regions of the semiconductor fin, and a source/drain feature disposed between the channel regions. The method also includes removing a portion of the first placeholder gate and a portion of the substrate directly disposed thereunder to form an isolation trench, forming a dielectric feature in the isolation trench, replacing the second placeholder gate with a metal gate stack, selectively recessing the dielectric feature, forming a first capping layer over the metal gate stack and a second capping layer over the recessed dielectric feature, and forming a source/drain contact over and electrically coupled to the source/drain feature.

Isolation structure and a self-aligned capping layer formed thereon

A semiconductor device structure includes nanostructures formed over a substrate. The structure also includes a gate structure formed over and around the nanostructures. The structure also includes a spacer layer formed over a sidewall of the gate structure over the nanostructures. The structure also includes a source/drain epitaxial structure formed adjacent to the spacer layer. The structure also includes a contact structure formed over the source/drain epitaxial structure with an air spacer formed between the spacer layer and the contact structure.

Semiconductor device structure and method for forming the same

Epitaxial source/drain structures for enhancing performance of multigate devices, such as fin-like field-effect transistors (FETs) or gate-all-around (GAA) FETs, and methods of fabricating the epitaxial source/drain structures, are disclosed herein. An exemplary device includes a dielectric substrate. The device further includes a channel layer, a gate disposed over the channel layer, and an epitaxial source/drain structure disposed adjacent to the channel layer. The channel layer, the gate, and the epitaxial source/drain structure are disposed over the dielectric substrate. The epitaxial source/drain structure includes an inner portion having a first dopant concentration and an outer portion having a second dopant concentration that is less than the first dopant concentration. The inner portion physically contacts the dielectric substrate, and the outer portion is disposed between the inner portion and the channel layer. In some embodiments, the outer portion physically contacts the dielectric substrate.

Epitaxial source/drain structures for multigate devices and methods of fabricating thereof

An interconnect fabrication method is disclosed herein that utilizes a disposable etch stop hard mask over a gate structure during source/drain contact formation and replaces the disposable etch stop hard mask with a dielectric feature (in some embodiments, dielectric layers having a lower dielectric constant than a dielectric constant of dielectric layers of the disposable etch stop hard mask) before gate contact formation. An exemplary device includes a contact etch stop layer (CESL) having a first sidewall CESL portion and a second sidewall CESL portion separated by a spacing and a dielectric feature disposed over a gate structure, where the dielectric feature and the gate structure fill the spacing between the first sidewall CESL portion and the second sidewall CESL portion. The dielectric feature includes a bulk dielectric over a dielectric liner. The dielectric liner separates the bulk dielectric from the gate structure and the CESL.

Dielectric structures for semiconductor device structures

A semiconductor structure and a method of forming the same are provided. An exemplary method of forming the semiconductor structure includes receiving a workpiece including a fin structure over a front side of a substrate, recessing a source region of the fin structure to form a source opening, extending the source opening into the substrate to form a plug opening, forming a semiconductor plug in the plug opening, planarizing the substrate to expose the semiconductor plug from a back side of the substrate, performing a first wet etching process to remove a portion of the substrate, performing a pre-amorphous implantation (PAI) process to amorphize a rest portion of the substrate, performing a second wet etching process to remove the amorphized rest portion of the substrate to form a dielectric opening, depositing a dielectric layer in the dielectric opening, and replacing the semiconductor plug with a backside source contact.

Method of forming backside power rails

A method of semiconductor fabrication includes providing a semiconductor structure having a substrate and first, second, third, and fourth fins above the substrate. The method further includes forming an n-type epitaxial source/drain (S/D) feature on the first and second fins, forming a p-type epitaxial S/D feature on the third and fourth fins, and performing a selective etch process on the semiconductor structure to remove upper portions of the n-type epitaxial S/D feature and the p-type epitaxial S/D feature such that more is removed from the n-type epitaxial S/D feature than the p-type epitaxial S/D feature.

Epitaxial source/drain structure and method

A semiconductor structure includes semiconductor fins disposed over a substrate, an epitaxial source/drain (S/D) feature disposed over the semiconductor fins, where a top surface portion of the epitaxial S/D feature includes two surfaces slanted downward toward each other at an angle, a silicide layer disposed conformally over the top portion of the epitaxial S/D feature, and an S/D contact disposed over the silicide layer, where a bottom portion of the S/D contact extends into the epitaxial S/D feature.

Methods of forming epitaxial source/drain features in semiconductor devices

A semiconductor device structure is provided. The semiconductor device structure includes a source/drain region formed in a semiconductor substrate, a source/drain contact structure formed over the source/drain region, and a gate electrode layer formed adjacent to the source/drain contact structure. The semiconductor device structure also includes a first spacer and a second spacer laterally and successively arranged from the sidewall of the gate electrode layer to the sidewall of the source/drain contact structure. The semiconductor device structure further includes a silicide region formed in the source/drain region. The top width of the silicide region is greater than the bottom width of the source/drain contact structure and less than the top width of the source/drain region.

Contact structure with silicide and method for forming the same

A semiconductor device and a method of forming the same are provided. In an embodiment, an exemplary semiconductor device includes two stacks of channel members; a source/drain feature extending between the two stacks of channel members along a direction; a source/drain contact disposed under and electrically coupled to the source/drain feature; two gate structures over and interleaved with the two stacks of channel members; a low-k spacer horizontally surrounding the source/drain contact; and a dielectric layer horizontally surrounding the low-k spacer.

Backside via with a low-k spacer

The present disclosure provides semiconductor devices and methods of forming the same. A semiconductor device according to one embodiment of the present disclosure includes a first fin-shaped structure extending lengthwise along a first direction over a substrate, a first epitaxial feature over a source/drain region of the first fin-shaped structure, a gate structure disposed over a channel region of the first fin-shaped structure and extending along a second direction perpendicular to the first direction, and a source/drain contact over the first epitaxial feature. The bottom surface of the gate structure is closer to the substrate than a bottom surface of the source/drain contact.

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Hsinchu, Taiwan

I-Wen Wu