United Microelectronics Corp.

I-Ming Lai

Chin-Cheng Chien

Chin-I Liao

Kun-Ju Li

Chau-Chung Hou

Wei-Xin Gao

Hsin-Jung Liu

Ang Chan

Teng-Chun Hsuan

Jhih-Yuan Chen

Zong-Sian Wu

Yu-Ren Wang

Chan-Lon Yang

Tsuo-Wen Lu

Tien-Wei Yu

Chien-Liang Lin

Shin-Chi Chen

Ching-I Li

Chih-Yueh Li

Fu-Shou Tsai

Shao-Wei Wang

Ger-Pin Lin

Wen-Yi Teng

Kuan-Yu Lin

Chun-Han Chen

Yun-San Huang

Fong-Lung Chuang

Tsung-Yu Hou

Hsiang-Chi Chien

A semiconductor assembly and a method for manufacturing the same are provided. The semiconductor assembly includes a first substrate, a first well in the first substrate and having a first doping type, a second substrate, a second well in the second substrate and having a second doping type, a first dielectric layer between the first substrate and the second substrate, and a second dielectric layer between the first substrate and the second substrate. The first doping type is different from the second doping type. The second dielectric layer is bonded to the first dielectric layer. The first well overlaps with the second well in a vertical direction.

Semiconductor assembly and method for manufacturing the same

A method for manufacturing a semiconductor device includes: providing a wafer-bonding stack structure having a sidewall layer and an exposed first component layer; forming a photoresist layer on the first component layer; performing an edge trimming process to at least remove the sidewall layer; and removing the photoresist layer. In this way, contaminant particles generated from the blade during the edge trimming process may fall on the photoresist layer but not fall on the first component layer, so as to protect the first component layer from being contaminated.

Method for manufacturing semiconductor device

First, a substrate with a recess is provided in a semiconductor process. Second, an embedded SiGe layer is formed in the substrate. The embedded SiGe layer includes an epitaxial SiGe material which fills up the recess. Then, a pre-amorphization implant (PAI) procedure is carried out on the embedded SiGe layer to form an amorphous region. Next, a source/drain implanting procedure is carried out on the embedded SiGe layer to form a source doping region and a drain doping region. Later, a source/drain annealing procedure is carried out to form a source and a drain in the substrate. At least one of the pre-amorphization implant procedure and the source/drain implanting procedure is carried out in a cryogenic procedure below &#x2212;30&#xb0; C.

Semiconductor process

A semiconductor device having epitaxial structures includes a gate structure positioned on a substrate, epitaxial structures formed in the substrate at two sides of the gate structure, and an undoped cap layer formed on the epitaxial structures. The epitaxial structures include a dopant, a first semiconductor material having a first lattice constant, and a second semiconductor material having a second lattice constant, and the second lattice constant is larger than the first lattice constant. The undoped cap layer also includes the first semiconductor material and the second semiconductor material. The second semiconductor material in the epitaxial structures includes a first concentration, the second semiconductor material in the undoped cap layer includes at least a first concentration, and the second concentration is lower than the first concentration.

Semiconductor device having epitaxial structures

A method for fabricating a compound semiconductor epitaxial structure includes the following steps. Firstly, a first compound epitaxial layer is formed on a substrate. Then, a continuous epitaxial deposition process is performed to form a second compound epitaxial layer on the first compound epitaxial layer, so that the second compound epitaxial layer has a linearly-decreased concentration gradient of metal. Afterwards, a semiconductor material layer is formed on the second compound epitaxial layer.

Compound semiconductor epitaxial structure and method for fabricating the same

A method for fabricating a metal oxide semiconductor (MOS) device is described, including following steps. Two recesses are formed in a substrate. A first epitaxy growth process is performed, so as to form a first semiconductor compound layer in each of the recesses. A second epitaxy growth process is performed with an epitaxial temperature lower than 700&#xb0; C., so as to form a cap layer on each of the first semiconductor compound layers. Each of the cap layers includes a second semiconductor compound layer protruding from a surface of the substrate. The first and the second semiconductor compound layers are composed of a first Group IV element and a second Group IV element, wherein the second Group IV element is a nonsilicon element. The content of the second Group IV element in the second semiconductor compound layers is less than that in the first semiconductor compound layers.

Method for fabricating first and second epitaxial cap layers

A test pattern for measuring semiconductor alloys using X-ray diffraction (XRD) includes a first region to an Nth region defined on a wafer, and a plurality of test structures positioned in the first region and so forth up to in the Nth region. The test structures in the same region have sizes identical to each other and the test structures in different regions have sizes different from each other.

Test pattern for measuring semiconductor alloys using X-ray Diffraction

A method of fabricating an epitaxial layer includes providing a substrate. The substrate is etched to form at least a recess within the substrate. A surface treatment is performed on the recess to form a Si&#x2014;OH containing surface. An in-situ epitaxial process is performed to form an epitaxial layer within the recess, wherein the epitaxial process is performed in a hydrogen-free atmosphere and at a temperature lower than 800&#xb0; C.

Method of fabricating an epitaxial layer

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Kaohsiung, Taiwan

I-Ming Lai