Taiwan Semiconductor Manufacturing Comp. Ltd.

I-Lun Tseng

Ting-Wei Chiang

Po-Hsiang Huang

Sheng-Hsiung Chen

Fong-yuan Chang

Jyun-Hao Chang

A method of designing a device includes identifying a pin to be inserted into a first layer of the device, wherein the first layer has a plurality of first routing tracks, and each of the plurality of first routing tracks extend in a first direction. The method further includes identifying a blocking shape on a second layer different from the first layer, wherein the second layer has a plurality of second routing tracks, and each of the plurality of second routing tracks extends in a second direction different from the first direction. The method further includes determining at least one candidate location for the pin in the first layer based on the plurality of first routing tracks of the first layer. The method further includes setting a location for the pin in the first layer based on the determined at least one candidate location.

Method of designing a device

A method of modifying a cell includes determining a number of pins in a maximum overlapped pin group region. The method further includes determining a number of routing tracks within a span region of the maximum overlapped pin group region. The method further includes comparing the number of pins and the number of routing tracks within the span region to determine a global tolerance of the cell. The method further includes increasing a length of at least one pin of the maximum overlapped pin group in response to the global tolerance failing to satisfy a predetermined threshold.

Method of modifying cell, system for modifying cell and global connection routing method

A method of modifying a cell includes identifying a maximum overlapped pin group. The method further includes determining a number of pins in the maximum overlapped pin group. The method further includes determining a span region of the maximum overlapped pin group. The method further includes comparing the number of pins and the span region to determine a global tolerance of the cell. The method further includes increasing a length of at least one pin of the maximum overlapped pin group in response to the global tolerance failing to satisfy a predetermined threshold. The method further includes fabricating a mask based on the increased length of the at least one pin.

Method of modifying cell and global connection routing method

A method of global connection routing includes determining a global connection tolerance of a cell for use in a circuit layout, wherein the cell comprises a plurality of pins, and a plurality of routing tracks are defined with respect to the cell. The method further includes determining a number of blocked tracks within the cell. The method further includes comparing the global connection tolerance with the number of blocked tracks. The method further includes adjusting a location of the cell within the circuit layout if the global connection tolerance and the number of blocked tracks fail to satisfy a predetermined condition.

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Hsinchu, Taiwan

I-Lun Tseng