Synopsys, Inc.

I-Jye Lin

Yao-Wen Chang

Tien-Chang Hsu

Po-Wei Lee

Hsien-Shih Chiu

Chun-Wei Lin

Chen-Feng Chang

Chin-Fang Shen

Gary K Yeap

Techniques for determining a density of through-silicon vias (TSVs) in a three-dimensional (3D) stacked die are disclosed. In some embodiments, such techniques may include obtaining first power consumption information associated with a first die of the 3D stacked die; obtaining second power consumption information associated with a second die of the 3D stacked die; identifying, on the first die, an area associated with the second die, the identified area overlapping an area associated with the first die; and determining a density of TSVs for the identified area based at least on the first power consumption information and the second power consumption information.

Determining a density of through-silicon vias in integrated circuits

Disclosed herein are rouging methods and devices for a flip-chip package. The flip chip includes several outer pads and several inner pads. The routing method includes: setting an outer sequence based on the arrangement order of the outer pads; setting several inner sequences based on the connection relationships between inner pads and the outer pads; calculating the longest common subsequence of each inner sequence and the outer sequence, defining the connection relationships between the inner pads and the outer pads corresponding to the longest common subsequence as direct connections, and defining the connection relationships between the inner pads and the outer pads that do not correspond to the longest common subsequence as detour connections; establishing the routing scheme of the flip chip based on the connection relationships between the inner pads and the outer pads.

Routing method for flip chip package and apparatus using the same

Growing community of inventors

Taipei, Taiwan

I-Jye Lin