Qualcomm Incorporated

University of California

Other

I-Hsiang Lin

Hiroshi Okabe

Tatsuo Itoh

Yi Zeng

Christophe Caloz

Tzu-Wang Pan

Liang Zhao

Pushp Trikha

Jeremy Darren Dunworth

Rahul A Apte

Zhijie Xiong

Bhushan Shanti Asuri

Aristotele Hadjichristos

Cheng-Han Wang

Prasad Srinivasa Siva Gudem

Roger Brockenbrough

Prashanth Akula

Kevin Hsi Huai Wang

Hong Sun Kim

Jin-Su Ko

Bahman Ahrari

Tg Vishwanath

Eugene Yang

Desong Zhao

Seshagiri Krishnamoorthy

A global navigation satellite system receiver with filter bypass mode for improved sensitivity is disclosed. In an aspect, an apparatus is provided that includes a non-bypass signal path coupled to a receiver, the non-bypass signal path comprising a filter. The apparatus also includes a bypass signal path coupled to the receiver, the bypass signal path configure to bypass the filter, and a switch to couple an antenna to the non-bypass signal path during time intervals when signals transmitted by an unrelated local transmitter are transmitted with a signal power that exceeds a selected threshold, and to couple the antenna to the bypass signal path during other time intervals.

Global navigation satellite system receiver with filter bypass mode for improved sensitivity

An RFIC configuration for reduced antenna trace loss is disclosed. In an exemplary embodiment, an apparatus includes a primary RFIC and a secondary RFIC that is configured to receive analog signals from at least two antennas. The secondary RFIC is configured to process selected analog signals received from at least one antenna to generate an analog output that is input to the primary RFIC.

RFIC configuration for reduced antenna trace loss

A receiver for a wireless device is described. The receiver includes a low noise amplifier that includes differential inputs. The receiver also includes a mixer coupled to the low noise amplifier. The receiver further includes second-order intermodulation reduction circuitry coupled to a stage subsequent to the low noise amplifier. The second-order intermodulation reduction circuitry provides a biasing of the differential inputs.

Reducing non-linearities in a differential receiver path prior to a mixer using calibration

Exemplary embodiments include a frequency modulation (FM) transmitter and a non-FM receiver, which may be implemented on the same IC chip. The FM transmitter may include a digital FM modulator, a lowpass filter, an amplifier, and an LC tank circuit. The digital FM modulator may receive a digital input signal, perform FM modulation with the digital input signal, and provide a digital FM signal. The lowpass filter may filter the digital FM signal and provide a filtered FM signal. The amplifier may amplify the filtered FM signal and provide an output FM signal. The LC tank circuit may filter the output FM signal. The digital FM modulator may perform FM modulation by changing a variable divider ratio of a multi-modulus divider within a PLL. A delta-sigma modulator may receive the digital input signal and generate a modulator output signal used to obtain the variable divider ratio.

FM transmitter and non-FM receiver integrated on single chip

Systematic IM2 calibration for a differential LNA is disclosed. In an aspect, an apparatus includes an amplifier configured to output an amplified signal having a level of systematic pre-mixer IM2 distortion, a detector configured to detect the level of the systematic pre-mixer IM2 distortion in the amplified signal, and a bias signal generator configured to generate at least one bias signal configured to adjust the amplifier to reduce the level of the systematic pre-mixer IM2 distortion.

Systematic intermodulation distortion calibration for a differential LNA

A frequency modulation (FM) transmitter implemented with a delta-sigma modulator and a phase-locked loop (PLL) is described. The delta-sigma modulator receives a modulating signal (e.g., an FM stereo multiplex (MPX) signal) and provides a modulator output signal. The PLL performs frequency modulation based on the modulator output signal and provides an FM signal. The FM transmitter may further include a gain/phase compensation unit and a scaling unit. The compensation unit may compensate the modulating signal for the closed-loop response of the PLL. The scaling unit may scale the amplitude of the modulating signal based on a gain to obtain a target frequency deviation for the FM signal. The PLL may operate in a transmit mode or a receive mode, may perform frequency modulation in the transmit mode, and may provide a local oscillator (LO) signal at a fixed frequency in the receive mode.

FM transmitter with a delta-sigma modulator and a phase-locked loop

A frequency synthesizer within an FM receiver employs a Phase-Locked Loop (PLL) to generate a Local Oscillator (LO) signal. The LO signal is supplied to a mixer. The FM receiver also includes jammer detection functionality. If no jammer is detected, then the loop bandwidth of the PLL is set to have a relatively high value, thereby favoring suppression of in-band residual FM. If a jammer is detected, then the loop bandwidth of the PLL is set to have a relatively low value, thereby favoring suppression of out-of-band SSB phase noise. By adaptively changing loop bandwidth depending on whether a jammer is detected, performance requirements on sub-circuits within the PLL can be relaxed while still satisfying in-band residual FM and out-of-band SSB phase noise requirements. By allowing the VCO of the PLL to generate more phase noise due to the adaptive changing of loop bandwidth, VCO power consumption can be reduced.

Jammer detection based adaptive PLL bandwidth adjustment in FM receiver

High-frequency couplers and coupling techniques are described utilizing artificial composite right/left-handed transmission line (CRLH-TL). Three specific forms of couplers are described; (1) a coupled-line backward coupler is described with arbitrary tight/loose coupling and broad bandwidth; (2) a compact enhanced-bandwidth hybrid ring coupler is described with increased bandwidth and decreased size; and (3) a dual-band branch-line coupler that is not limited to a harmonic relation between the bands. These variations are preferably implemented in a microstrip fabrication process and may use lumped-element components. The couplers and coupling techniques are directed at increasing the utility while decreasing the size of high-frequency couplers, and are suitable for use with separate coupler or couplers integrated within integrated devices.

Composite right/left (CRLH) couplers

An FM radio with a wide frequency range operates in a cell phone without interfering with the VCO of the RF transceiver. The FM transceiver generates a VCO signal whose frequency varies by less than &#xb1;7% from the midpoint of a narrow first range. A synthesizer signal is generated by dividing the VCO frequency by a first divisor such that the synthesizer frequency varies over a lower frequency second range. The VCO frequency is also divided by a second divisor such that the synthesizer frequency varies over a third range. The upper limit of the second range falls at the lower limit of the third range. The lower limit of the second range is 85.5 MHz and the upper limit of the third range is 108.0 MHz. By also using a third divisor, a synthesizer signal with a range of 76-108 MHz is generated from the narrow first frequency range.

FM radio frequency plan using programmable output counter

A VCO (for example, in an FM receiver) includes an LC resonant tank. The LC resonant tank includes a coarse tuning capacitor bank and a fine tuning capacitor bank. The coarse tuning capacitor bank contains a plurality of digitally controlled coarse tuning capacitor elements, each providing a first capacitance value when active. The fine tuning capacitor bank contains a plurality of digitally controlled fine tuning capacitor elements, each providing a second capacitance value when active. To address the practical problem of capacitor mismatch, capacitance overlap throughout the VCO tuning range is created by selecting the first and second capacitance values such that the capacitance value of the fine capacitor bank is greater than the first capacitance value when all of the digitally controlled fine tuning capacitor elements of the fine capacitor bank are active.

Overlapping, two-segment capacitor bank for VCO frequency tuning

A clock clean-up phase-locked loop (PLL) that may reduce spurs and improve performance of a receiver is described. In one exemplary design, an integrated circuit includes a PLL and an analog-to-digital converter (ADC). The PLL receives a first clock signal generated with a fractional divider ratio and having spurs due to abrupt frequency jumps. The first clock signal may be generated by a fractional-N frequency synthesizer external to the integrated circuit. The PLL generates a second clock signal with an integer divider ratio and having reduced spurs. The ADC digitizes an analog baseband signal based on the second clock signal and provides digital samples. The integrated circuit may further include a low noise amplifier (LNA), which may observe less spurs coupled via the substrate of the integrated circuit due to the use of the PLL to clean up the first clock signal.

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Mountain View, CA, United States of America

I-Hsiang Lin