Realtek Semiconductor Inc.

I-Hao Chiang

The present disclosure discloses a content addressable memory apparatus. A self-test control circuit generates self-test driving signals and control an external test pattern generation circuit generates search data and an address signal. A content addressable memory circuit includes a memory circuit, an internal test pattern generation circuit and an internal comparison circuit. The memory circuit receives the search data and the address signal from the external test pattern generation circuit to perform search operation to generate actual match signals corresponding to the match lines. The internal test pattern generation circuit receives the self-test driving signals from the self-test control circuit to generate expected match signals. The internal comparison circuit receives and compares the actual match signals and the expected match signals to generate match comparison results such that the self-test control circuit receives the match comparison results and performs verification accordingly.

Content addressable memory apparatus, content addressable memory circuit and memory self-test method thereof

A masking circuit of a content addressable memory (CAM) includes a masking control circuit and a level control circuit. The masking control circuit generates a masking signal according to a word line (WL) signal and a write enablement (WE) signal. When both the WL and WE signals are at a first level, the masking signal is a first masking signal; when they are at different levels respectively, the masking signal is a second masking signal. The level control circuit generates a level control signal according to the masking signal for determining whether to pull a voltage level of a match line of the CAM to a predetermined level. When the masking signal is the first masking signal, the level control circuit pulls the voltage level to the predetermined level; and when the masking signal is the second masking signal, the level control circuit does not interfere in the voltage level.

Masking circuit and pre-charge circuit applicable to content addressable memory

A content addressable memory (CAM) device includes first to third CAM circuits and first to second peripheral circuits. The first CAM circuit stores a first bit of a first word. The second CAM circuit is arranged adjacent to the first CAM circuit and stores a first bit of a second word. The third CAM circuit is arranged adjacent to the second CAM circuit and store a second bit of the second word. The first to the third CAM circuits are arranged in a memory row. The first peripheral circuit accesses the first bits in the first and the second words. The second peripheral circuit accesses the second bit of the second word.

Area efficient content addressable memory device

A content addressable memory cell includes storage circuits and a comparator circuit. A first storage circuit of the storage circuits is configured to store data, and a second storage circuit of the storage circuits is configured to store a state bit. The comparator circuit is configured to determine whether to adjust a level of a match line to a level of one of the data and the state bit in response to levels of search bit lines and another one of the data and the state bit.

Content addressable memory cell

A time-division memory control device controls a content addressable memory (CAM) cell array of a CAM in a time-division manner and thereby reduces a peak current and mitigates electromigration and voltage variation problems. The time-division memory control device includes a time-division controller and a peripheral circuit. In a search and compare operation, the time-division controller outputs a first group of control signals at a first time point according to a system clock, and outputs a second group of control signals at a second time point later than the first time point. The peripheral circuit includes: a first group of circuits cooperating with a first group of CAM cells of the CAM cell array according to the first group of control signals; and a second group of circuits cooperating with a second group of CAM cells of the CAM cell array according to the second group of control signals.

Time-division memory control device

A memory device includes a controller circuit, a first stage circuit, and a second stage circuit. The controller circuit outputs a first global pre-charge control signal, a second global pre-charge control signal, and a first local pre-charge control signal. The first stage circuit pre-charges a first global match line according to the first global pre-charge control signal, and to compare search data with first data, in order to determine whether to adjust a first level of the first global match line. The second stage circuit selectively pre-charges a second global match line according to the first level and the second global pre-charge control signal, and determines whether to compare the search data with second data according to a second level of the second global match line and the first local pre-charge control signal, in order to adjust the second level.

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Hsinchu, Taiwan

I-Hao Chiang