Au Optronics Corporation

I-Chun Chen

Chu-Yu Liu

Chou-Chin Wu

Kuei-Sheng Tseng

Ming-Hung Shih

Po-Jen Chiang

Yu-Chieh Kuo

Tung-Chang Tsai

Jen-Wen Wan

Hui-Ting Hsu

An active device array substrate including a first patterned conductive layer, a dielectric layer, a second patterned conductive layer, a passivation layer and pixel electrodes is provided. The first patterned conductive layer includes scan lines, common lines, gates and strip floating shielding patterns. The dielectric layer covering the first patterned conductive layer has first contact holes which expose a portion of the common lines, respectively. The second patterned conductive layer includes data lines, sources, drains and strip capacitance electrodes. Each strip capacitance electrode is electrically connected to one of the common lines through one of the first contact holes. A gap is formed between each data line and one strip capacitance electrode, and the strip floating shielding patterns are disposed under the data lines, the gap and the strip capacitance electrodes. Each pixel electrode is electrically connected to one of the drains through one of the second contact holes.

Active device array substrate

A liquid crystal display panel and liquid crystal display array substrate are disclosed. The liquid crystal display array substrate includes first scan lines, second scan lines, data lines, first columns of pixel units and second columns of the pixel units. Each of the first columns of the pixel units has a plurality of first pixel structures electrically connected to the first scan lines and the data lines respectively. Each of the second columns of the pixel units has a plurality of second pixel structures electrically connected to the second scan lines and the data lines respectively. Each of the first pixel structures has a first storage capacitor, and the first storage capacitor has a first capacitance value. Each of the second pixel structures has a second storage capacitor, and the second storage capacitor has a second capacitance value, wherein the second capacitance value is less than the first capacitance value.

Liquid crystal display panel and liquid crystal display array substrate

A pixel array includes pixel sets. Each pixel set includes a first and second scan lines arranged in parallel on a substrate, a data line not parallel to the first and second scan lines, a first active device electrically connecting the first scan line and the data line, a second active device electrically connecting the second scan line and the data line, a first pixel electrode electrically connecting the first active device, a second pixel electrode electrically connecting the second active device, and an auxiliary electrode pattern that includes a connecting portion and a first and second branch portions. A gap is between the first and second pixel electrodes. The connecting portion underneath the gap between the first and second pixel electrodes partially overlaps the first and second pixel electrodes. The first and second branch portions connect the connecting portion and partially overlap the first and second pixel electrodes, respectively.

Pixel array

A liquid crystal display panel and liquid crystal display array substrate are disclosed herein. The liquid crystal display array substrate includes scan lines, data lines, first rows of pixel units, and second rows of pixel units. The first rows of pixel units and the second rows of pixel units are arranged alternately. Each of the first rows of pixel units has first pixel structures disposed in a row direction and electrically connected to the scan lines and the data lines, respectively. Each of the second rows of pixel units has second pixel structures disposed along the row direction and electrically connected to the scan lines and the data lines, respectively. The first capacitance value of the first storage capacitor of each first pixel structure is greater than the second capacitance value of the second storage capacitor of each second pixel structure.

A liquid crystal display and a shift register device thereof are provided. The shift register device includes a plurality of shift registers connected in series. In the invention, the channel lengths of the transistors, which are responsible to stop outputting scan signal, in the shift register are manufactured greater than the channel lengths of the transistors, which are responsible to output the scan signal, in the shift register. As a result, the degree of influence that the leakage currents of the N-type transistors being responsible to stop outputting the scan signal in the shift register affect the transistors being responsible to output the scan signal when the transistors being responsible to stop outputting the scan signal are in the sub-threshold region is reduced. And thus each of the shift registers is able to output the scan signal normally.

Growing community of inventors

Taoyuan County, Taiwan

I-Chun Chen