Macronix International Co., Ltd.

I-Ching Tseng

Hsiang-Pang Li

Hung-Sheng Chang

Han-Wen Hu

Chia-Lin Yang

Hsiang-Yun Cheng

Tzu-Hsien Yang

A computation method and a computation apparatus exploiting weight sparsity, adapted for a processor to perform multiply-and-accumulate operations on a memory including multiple input and output lines crossing each other. In the method, weights are mapped to the cells of each operation unit (OU) in the memory. The rows of the cells of each OU are compressed by removing at least one row of the cells each mapped with a weight of 0, and an index including values each indicating a distance between every two rows of the cells including at least one cell mapped with a non-zero weight for each OU is encoded. Inputs are inputted to the input lines corresponding to the rows of each OU excluding the rows of the cells with the weight of 0 according to the index and outputs are sensed from the output lines corresponding to the OU to compute a computation result.

Growing community of inventors

Taipei, Taiwan

I-Ching Tseng