Realtek Semiconductor Inc.

I-Ching Tsai

Yun-Chih Chang

Shu-Yi Kao

Li-Yi Lin

En-Cheng Liu

An IC design method is provided that includes steps outlined below. A clock tree structure is retrieved from an IC design file. A branch level number of a branch that each of clock units in the clock tree structure locates is determined. A common branch level number of a common branch that closest to each two of the flip-flops is determined. A scan chain structure is retrieved from the IC design file. A wire distance and a clock skew of each two of the flip-flops are determined. A cost is calculated according to the common branch number, the wire distance and the clock skew. An initial point and a terminal point of the flip-flops in the scan chain structure are determined to further calculate a path having a minimum cost. The order of the scan chain structure of the IC design file is updated.

Integrated circuit design method and non-transitory computer readable medium thereof

The invention discloses a clock tree synthesis method including steps of: determining a driving strength of a clock cell; determining a reserved space corresponding to the clock cell according to the driving strength; generating the clock cell and the reserved space, wherein the reserved space is adjacent to the clock cell; setting a decoupling capacitor filler cell in the reserved space, wherein the area and/or capacitance of the decoupling capacitor filler cell are/is associated with the driving strength; and fixing the attribute(s) of the clock cell and the attribute(s) of the decoupling capacitor filler cell.

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Hsinchu, Taiwan

I-Ching Tsai